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HT36M4 датащи(PDF) 7 Page - Holtek Semiconductor Inc

номер детали HT36M4
подробное описание детали  Music Synthesizer 8-Bit MCU
PDF  24 Pages
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производитель  HOLTEK [Holtek Semiconductor Inc]
домашняя страница  http://www.holtek.com
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HT36M4 датащи(HTML) 7 Page - Holtek Semiconductor Inc

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HT36M4
Rev. 1.10
7
March 14, 2007
· Bank pointer
The program memory is organized into 8 banks and
each bank into 8192
´16 of bits program ROM. PF2~
PF0 is used as the bank pointer. After an instruction
has been executed to write data to the PF register to
select a different bank, note that the new bank will not
be selected immediately. The new bank is only se-
lected after an instruction cycle is executed. When the
PF register is used to select the bank, the PF register
is write only. It is not until the following instruction has
completed execution that the bank will be actually se-
lected. It should be note that the PF register is write
only.
Wavetable ROM
The ST11~ST0 are used to defined the start address of
each sample on the wavetable and read the waveform
data from the location. HT36M4 provides 17 output ad-
dress lines from WA16~WA0, the ST11~ST0 are used
to locate the major 12 bits i.e. WA16~WA5 and the un-
defined data from WA4~WA0 are always set to 00000b.
So the start address of each sample have to be located
at a multiple of 32 bytes. Otherwise, the sample will not
be read out correctly because it has a wrong starting
code.
Stack Register
- Stack
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the Stack Pointer will point to
the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subse-
quently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return ad-
dress are stored).
Data Memory
- RAM
The data memory is designed with 2
´256´8 bits. The
data memory is divided into three functional groups:
special function registers, wavetable function register,
and general purpose data memory (2
´192´8). Most of
them are read/write, but some are read only.
S p e c i a l P u r p o s e
D a t a M e m o r y
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 9 H
2 A H
2 B H
3 F H
: U n u s e d .
R e a d a s " 0 0 "
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
M P 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
M P 1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
I N T C
T M R 0 H
T M R 0 L
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P F
D A H
C h a n n e l n u m b e r s e l e c t
F r e q u e n c y n u m b e r h i g h b y t e
F r e q u e n c y n u m b e r l o w b y t e
S t a r t a d d r e s s h i g h b y t e
S t a r t a d d r e s s l o w b y t e
R e p e a t n u m b e r h i g h b y t e
R e p e a t n u m b e r l o w b y t e
C o n t r o l r e g i s t e r
R i g h t v o l u m c o n t r o l
2 8 H
W a v e t a b l e F u n c t i o n
R e g i s t e r
D A L
D A C
B P
F F H
4 0 H
G e n e r a l P u r p o s e
D a t a M e m o r y
( 1 9 2
´ 2 B y t e s )
B a n k 0
B a n k 1
RAM Mapping



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