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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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440SP датащи(PDF) 79 Page - Applied Micro Circuits Corporation |
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440SP датащи(HTML) 79 Page - Applied Micro Circuits Corporation |
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79 / 85 page  PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 79 Data Sheet DDR SDRAM Clock to Write DQS Timing—TDS Note 1: All of the DQS signals are referenced to MemClkOut. Note 2: Clock speed is 333 MHz. Note 3: The TDS values in the table include 1.5 × 3ns cycle at 333 MHz (3 ns × 1.5 = 4.5 ns). Note 4: To obtain adjusted values for lower clock frequencies, subtract 4 ns from the values in the following table and add × 1.5 of the cycle time for the lower clock frequency (T DS - 4.5 + 1.5 TCYC). DDR SDRAM Write Data to DQS Timing—TSD and THD Note 1: TSD and THD are measured under worst-case conditions. Note 2: Clock speed for the values in the following table is 333 MHz. Table 18. DDR SDRAM Clock to Write DQS Timing—TDS Signal Name TDS (ns) Minimum Maximum DQS0 4.76 5.07 DQS1 4.78 5.09 DQS2 4.78 5.10 DQS3 4.76 5.07 DQS4 4.79 5.11 DQS5 4.80 5.13 DQS6 4.81 5.11 DQS7 4.79 5.11 DQS8 4.77 5.07 Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD Signal Name Reference Signal TSD (ns) THD (ns) MemData00:07, DM0 DQS0 0.58 0.64 MemData08:15, DM1 DQS1 0.62 0.55 MemData16:23, DM2 DQS2 0.62 0.60 MemData24:31, DM3 DQS3 0.63 0.57 MemData32:39, DM4 DQS4 0.68 0.54 MemData40:47, DM5 DQS5 0.67 0.52 MemData48:55, DM6 DQS6 0.62 0.61 MemData56:63, DM7 DQS7 0.65 0.55 ECC0:7, DM8 DQS8 0.63 0.61 |
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