PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

AMCC

39

Data Sheet

Strapping

When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to

enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest SysClk edge

before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down

(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k

Ω to +3.3V or 10kΩ to

+5V. The recommended pull-down is 1K

Ω to GND. These pins are use for strap functions only during reset. They

are used for other signals during normal operation. The following table lists the strapping pins along with their func-

tions and strapping options. The signal names assigned to the pins for normal operation follow the pin number.

Table 16. Strapping Pin Assignments (Sheet 1 of 2)

Function

Option

Ball Strapping

for 6

for 7 < M

for 12 < M

See Note.

W15

UART0_Tx

U13

UART0_DTR

V20

UART0_RTS

Choice 1; TUNE[5:0] = 010001

0

0

0

Choice 2; TUNE[5:0] = 010010

0

0

1

Choice 3; TUNE[5:0] = 010011

0

1

0

Choice 4; TUNE[5:0] = 010100

0

1

1

Choice 5; TUNE[5:0] = 010101

1

0

0

Choice 6; TUNE[5:0] = 010110

1

0

1

Choice 7; TUNE[5:0] = 010111

1

1

0

Choice 8; TUNE[5:0] = 100100

1

1

1

C16

DMAAck0

B17

DMAAck1

Bypass mode

0

0

Divide by 3

0

1

Divide by 4

1

0

Divide by 6

1

1

B16

DMAAck2

A14

DMAAck3

Divide by 1

0

0

Divide by 2

0

1

Divide by 3

1

0

Divide by 4

1

1

B18

GPIO1[TS1E]

D16

GPIO2[TS2E]

Divide by 1

0

0

Divide by 2

0

1

Divide by 3

1

0

Divide by 4

1

1

T4

HoldAck

U5

ExtAck

Divide by 1

0

0

Divide by 2

0

1

Divide by 3

1

0

Divide by 4

1

1