FM24CL16

Rev 3.3

Nov. 2005

Page 2 of 13

Address

Latch

`

256 x 64

FRAM Array

Data Latch

8

SDA

Counter

Serial to Parallel

Converter

Control Logic

SCL

WP

Figure 1. Block Diagram

Pin Description

Pin Name

Type

Pin Description

SDA

I/O

Serial Data Address: This is a bi-directional data pin for the two-wire interface. It

employs an open-drain output and is intended to be wire-OR’d with other devices on the

two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the

output driver includes slope control for falling edges. A pull-up resistor is required.

SCL

Input

Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on

the falling edge and clocked-in on the rising edge.

WP

Input

Write Protect: When WP is high, the entire array is write-protected. When WP is low,

all addresses may be written. This pin is internally pulled down.

VDD

Supply

Supply Voltage (3V)

VSS

Supply

Ground

NC

-

No connect