The fcCSP package is assembled on a laminate or mold-based substrate

with or without a core. The package is processed in strip format for

manufacturing efficiency and to minimize cost and enables bare die,

overmolded and exposed die structures. The thermal challenges of high-

power devices can be managed by applying an integrated heat spreader.

Antenna in Package (AiP) can be enabled with the use of bottom side chip

attach (POSSUM™). Finally, when coupled with copper pillar bumped die,

fcCSP technology takes advantage of fine line/space substrate routing

and bump pitch to reduce layer count and cost while increasing electrical

performance.

Features

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Suitable for low and high-frequency applications

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Low inductance of flip chip bumps – short, direct signal path

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No technological limitation to BGA ball count

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Target markets – mobile (AP, BB, RF, PMIC), automotive, consumer,

connectivity, multi-die (side-by-side or stacked) applications requiring

high-routing density

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Custom package sizes and shapes with strip-based processing

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Coreless, thin core, laminate and molded substrate construction

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Bare die, overmolded, exposed die molded constructions

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Accommodates package sizes from 1 x 1 mm2 to 25 x 25 mm2

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Bump pitches down to 50 µm in-line and 30/60 µm staggered

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BGA ball pitches down to 0.3 mm

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Package thicknesses down to 0.35 mm

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Turnkey solutions – design, bumping, wafer probe, assembly, final test

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Exposed die molding available for low-profile and thermal applications

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Heat spreader attach available for high-power devices

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Bottom side chip attach available for AiP applications (POSSUM™)

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Mass reflow and thermal compression chip attach available

Amkor Technology offers the Flip Chip CSP (fcCSP) package – a flip

chip solution in a CSP package format. This package construction

can be used with all of Amkor’s available bumping options (copper

pillar, Pb-free solder, eutectic), while enabling flip chip interconnect

technology in area array and, when replacing standard wirebond

interconnect, in a peripheral bump layout. There are multiple

advantages to flip chip interconnect; it provides enhanced electrical

performance over standard wirebond technology, it allows for a

smaller form factor due to increased routing density and it eliminates

the z-height impact of wirebond loops.

Flip Chip CSP (fcCSP)

DATA SHEET | LAMINATE PRODUCTS

APPLICATIONS

The fcCSP package is an attractive

option for applications in which

both performance and form factor

are critical. Examples include

high-performance mobile devices

(including 5G), infotainment and

ADAS for automotive and AI. Further,

the benefits from low inductance

and increased routing density enable

optimized electrical paths for high-

frequency signals, making fcCSP

suitable for Baseband, RF and

in-substrate antenna applications.

PROCESS HIGHLIGHTS

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Die size: 0.5 x 0.5 mm2 to 16 x 16 mm2

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Package size: 1 x 1 mm2 to 25 x 25 mm2

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Bump pitch (LF or eutectic)

▷ As low as: 80 μm

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Bump pitch (Cu pillar)

▷ As low as: 30/60 μm