SC1155 datasheet(12/20 Pages) SEMTECH

12 / 20 page

 2001 Semtech Corp.

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POWER MANAGEMENT

SC1155

PRELIMINARY

Reference/Voltage Identification

The reference/voltage identification (VID) section con-

sists of a temperature compensated bandgap reference

and a 5-bit voltage selection network. The 5 VID pins

are TTL compatable inputs to the VID selection network.

They are internally pulled up to +5V generated from the

+12V supply by a resistor divider, and provide program-

mability of output voltage from 1.1V to 1.8V in 25mV

increments.

Refer to the Output Voltage Table for the VID code set-

tings. The output voltage of the VID network, VRE. is

within 1% of the nominal setting over the full input and

output voltage range and junction temperature range.

The output of the reference/VID network is indirectly

brought out through a buffer to the RE.B pin. The volt-

age on this pin will be within 3mV of VRE.. It is not rec-

ommended to drive loads with RE.B other than setting

the hysteresis of the hysteretic comparator, because the

current drawn from RE.B sets the charging current for

the soft start capacitor. Refer to the soft start section

for additional information.

Hysteretic Comparator

The hysteretic comparator regulates the output voltage

of the synchronous-buck converter. The hysteresis is

set by connecting the center point of a resistor divider

from RE.B to AGND to the HYST pin. The hysteresis of

the comparator will be equal to twice the voltage differ-

ence between RE.B and HYST, and has a maximum value

of 60mV. The maximum propagation delay from the com-

parator inputs to the driver outputs is 250ns.

Low Side Driver

The low side driver is designed to drive a low R

DS(ON) N-

channel MOS.ET, and is rated for 2 amps source and

sink. The bias for the low side driver is provided inter-

nally from VDRV.

High Side Driver

The high side driver is designed to drive a low R

DS(ON) N-

channel MOS.ET, and is rated for 2 amps source and

sink. It can be configured either as a ground referenced

driver or as a floating bootstrap driver. When configured

as a floating driver, the bias voltage to the driver is de-

veloped from the DRV regulator. The internal bootstrap

Applications Information - .unctional Description

diode, connected between the DRV and BOOT pins, is a

Schottky for improved drive efficiency. The maximum

voltage that can be applied between the BOOT pin and

ground is 25V. The driver can be referenced to ground

by connecting BOOTLO to PGND, and connecting +12V

to the BOOT pin.

Deadtime Control

Deadtime control prevents shoot-through current from

flowing through the main power .ETs during switching

transitions by actively controlling the turn-on times of the

.ET drivers. The high side driver is not allowed to turn on

until the gate drive voltage to the low-side .ET is below 2

volts, and the low side driver is not allowed to turn on

until the voltage at the junction of the 2 .ETs (VPHASE) is

below 2 volts. An internal low-pass filter with an 11MHz

pole is located between the output of the low-side driver

(DL) and the input of the deadtime circuit that controls

the high-side driver, to filter out noise that could appear

on DL when the high-side driver turns on.

Current Sensing

Current sensing is achieved by sampling and holding the

voltage across the high side .ET while it is turned on.

The sampling network consists of an internal 50Ω switch

and an external 0.1µ. hold capacitor. Internal logic con-

trols the turn-on and turn-off of the sample/hold switch

such that the switch does not turn on until VPHASE tran-

sitions high and turns off when the input to the high side

driver goes low. Thus sampling will occur only when the

high side .ET is conducting current. The voltage at the

IO pin equals 2 times the sensed voltage. In applica-

tions where a higher accuracy in current sensing is re-

quired, a sense resistor can be placed in series with the

high side .ET and the voltage across the sense resistor

can be sampled by the current sensing circuit.

Droop Compensation

The droop compensation network reduces the load tran-

sient overshoot/undershoot at VOUT, relative to VRE..

VOUT is programmed to a voltage greater than VRE. equal

to VRE. (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an

external resistor divider from VOUT to the VSENSE pin to

reduce the undershoot on VOUT during a low to high load

current transient. The overshoot during a high to low

load current transient is reduced by subtracting the volt-

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