MIC2132 datasheet(28/48 Pages) MICROCHIP

28 / 48 page

MIC2132

DS20006654B-page 28

 2022 Microchip Technology Inc. and its subsidiaries

FIGURE 4-17:

Use of an NTC Resistance

to Compensate the RDSON Temperature

Coefficient on the DROOP Pin.

The idea in Figure 4-17 is that increasing DROOP

voltage with temperature at the IOUT(MAX) (positive

temperature coefficient) is compensated by the RNTC

(negative temperature coefficient) to keep the node of

the divider, Div_DROOP_ZeroTC, constant versus

temperature.

The rest of the calculations are similar to the afore-

mentioned case where the sensing current was

temperature-insensitive. In case the AVP is not

necessary, a 10 kΩ, 1 nF series RC filter to ground can

be used to have a reading of the filtered output current.

4.5.10

MULTIPHASING (STACKING)

The MIC2132 can be configured for multiphase

operation of up to eight phases. The MIC2132 has four

pins allocated for multiphasing. The APO pin of the

host controller is connected to the NPI pin of the next

secondary controller. The host and secondary CSH,

ONR pins are connected together. Once the host

finishes the on requests, it passes the control to the

next secondary through the APO pin. The current share

bus will maintain equal current sharing between host

and secondary controllers.

The ONR is a bidirectional pin. The desired secondary

controller’s FBS pin is connected to VDD to program

the controller as secondary. This will make the ONR pin

of the secondary controller become input only. Second-

ary controllers accept ONR from the host controller and

serve the on-time request.

Figure 4-18 shows two MIC2132 devices connected in

a 4-phase configuration. The NPI and APO pins of the

MIC2132 are connected in a daisy-chain to form a

stackable power supply up to eight phases.

FIGURE 4-18:

MIC2132 Connected in

4-Phase Configuration.

In order to get a stricter control over behavior if one

member of the daisy-chain is damaged or going to be

damaged, or is in short or thermal shutdown, several

measures were implemented.

The host is the only one programming the ILIM.

The secondaries are just reading the voltage on

ILIM; as a common point, they do not have any

programming current coming out.

The soft start pin is driven up with 1.2 µA from all

members of the daisy-chain. When any of the

members of the daisy-chain pulls down the SS

pin in case of thermal shutdown, or short circuits

more than seven cycles, a new automatic restart

is triggered on the falling edge of SS. Any of the

daisy-chain members can keep low closed to 0

in the SS pin, and in that case, all members are

in High-Z and wait until SS is released to go up.

To illustrate if one member has the LDO not

coming up, this will keep the SS pin in low.

To ensure that some timing mismatch between

chips is not creating a disorderly start, the delay

in the block, BiasReadyGen, is 3 ms for the host

and 1.5 ms (half) for the secondaries. The 3 ms

and 1.5 ms time frames are the result of the

activity of a local oscillator and counter.

MIC2132

FBS

RFBB1

DROOP

VOUT

RINJ

CINJ

RIP_INJ

GFB

RDROOP

RFBB2

RFBT

CFF

RNTC

Div_DROOP_ZeroTC

RBIAS

MIC2132

Host

CSH

ONR

APO

NPI

FBS

GFB

RIP_INJ

MIC2132

Secondary

CSH

ONR

APO

NPI

FBS

GFB

RIP_INJ

VOUT

VDD

DH1

SW1

DL1

DH2

SW2

DL2

DH1

SW1

DL1

DH2

SW2

DL2

MIC2132 Connected in 4-Phase Configuration

ILIM

MIC2132 датащи(PDF) 28 Page - Microchip Technology

MIC2132 датащи(HTML) 28 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL