MCP16501 datasheet(24/42 Pages) MICROCHIP

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MCP16501

DS20006388E-page 24

 2020-2022 Microchip Technology Inc. and its subsidiaries

FIGURE 4-8:

Entering Hibernate Mode

Timing Diagram.

From the Hibernate state, the system can:

Move to OFF state (if LPM also goes low, the

VOUT2 can be immediately turned off); or

Initiate another start-up sequence (with the

exception of Buck2 which is already active) by a

low-to-high transition of PWRHLD.

The timing diagram of a start-up sequence from Hibernate

mode is shown in Figure 4-9. After the assertion of

PWRHLD, the MPU may deassert LPM at any time. Due

to internal filtering, simultaneous transition of LPM and

PWRHLD is allowed (hold time t5 can be 0 µs).

Depending on the time at which LPM is deasserted, the

MCP16501 may transition through the Low-Power

state or not.

FIGURE 4-9:

Start-Up Sequence Exiting

Hibernate Mode Timing Diagram.

Where:

t5 = Setup time, LPM = 1 to PWRHLD = 0:

Min. 0 µs (internal filtering applies)

t6 = Delay from PWRHLD deasserted to

nRSTO asserted: Min. 0 µs,

max. 10 µs (not a strict requirement)

t7 = Delay from nRSTO asserted to first

VOUTX turn-off: Min. 0 µs, max. 10 µs

(not a strict requirement)

Note:

Upon exit of Hibernate mode, Buck2 is not

part of the sequence because it is already

turned on (being in Auto-PFM mode).

However, also depending on the instant at

which the MPU deasserts LPM, it can tog-

gle to FPWM mode at the time nRSTO is

deasserted.

Where:

t1 = Delay from PWRHLD asserted to first

supply VOUT1 starting (default 0.5 ms)

t3 =Time from VOUT1 established to VOUT3

starting (default 4 ms)

t4 =Time from VOUT3, established to

nRSTO deassertion (default 16 ms)

t5 = Minimum hold time, PWRHLD = 1 to

LPM = 0: Min. 0 µs (internal filtering

applies)

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