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LRCK

PCM4220

PCM4220

AudioDSP

or

Interface

AudioDSP

or

Interface

BCK

DATA

LRCK

BCK

DATA

MCKI

MCLK

MCKI

MCLK

Master

Clock

Master

Clock

(a)SlaveMode(S/M=HI)

(b)MasterMode(S/M=LO)

FSYNC

SCLK

DATA

FSYNC

SCLK

DATA

PCM4220

SBAS407A – DECEMBER 2006 – REVISED MAY 2007

LRCK clock is an input, with the rate set by an external audio bus master (that is, a clock generator, digital

signal processor, etc.). In Master mode, the LRCK clock is an output, derived from the master clock input using

on-chip clock dividers (as is the BCK clock). The clock divider is configured using the FS0 and FS1 pins, which

are discussed in the PCM Output and Sampling Modes section of this datasheet.

For the TDM data formats, the BCK rate depends upon the sampling mode for either Slave or Master operation.

Normal mode, four for Double Rate mode, and two for Quad Rate mode.

When using the TDM formats, the sub-frame assignment for the device must be selected using the SUB0 and

SUB1 inputs (pins 26 and 25, respectively). Table 4 summarizes the sub-frame selection options. A sub-frame

contains two 32-bit time slots, with each time slot carrying 24 bits of audio data corresponding to either the left or

right channel of the PCM4220. Refer to Figure 41 through Figure 43 for TDM interfacing connections and

sub-frame formatting details. For the TDM format with one BCK delay, the serial data output is delayed by one

BCK period after the rising edge of the LRCK clock.

Table 4. TDM Sub-frame Assignment

SUB1 (pin 25)

SUB0 (pin 26)

SUB-FRAME ASSIGNMENT

LO

LO

Sub-frame 0

LO

HI

Sub-frame 1

HI

LO

Sub-frame 2

HI

HI

Sub-frame 3

When using TDM formats with Double Speed sampling, it is recommended that the SUB1 pin be forced low.

When using TDM formats with Quad Speed sampling, it is recommended that both the SUB0 and SUB1 pins be

forced low.

For all serial port modes and data formats, when driving capacitive loads greater than 30pF with the data and

clock outputs, it is recommended that external buffers be utilized to ensure data and clock integrity at the

receiving device(s).

For specifications regarding audio serial port operation, the reader is referred to the Electrical Characteristics:

Audio Interface Timing table, as well as Figure 1 and Figure 2 in this data sheet.

Figure 39. Slave and Master Mode Operation

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