ST10F269ZX datasheet(183/184 Pages) STMICROELECTRONICS

183 / 184 page

ST10F269

3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION

183/184

2.4 - ST_PORT.3 - Bad Behavior of Hysteresis Function on Input Falling Edge

In the following conditions, a slow falling edge on a ST10F269 input may generate multiple events :

– A falling edge is occuring.

– AND the falling edge has a transition time between Vih and Vil longer than the CPU clock period.

Workaround:

Add external hardware on the ST10 input in order to have a fast falling edge (lower than 1/Fcpu).

History of Fixed Functional Problems of the ST10F269Zxxx-D

Summary of Remaining Functional Problems Known on the ST10F269Zxxx-D

3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION

Note on on-chip oscillator

The XTAL2 output is not designed to provide a valid signal when XTAL1 is supplied by an external clock

signal. It may happen, if the external clock signal is not perfectly symetrical and centered on VDD / 2, that

XTAL2 signal is not equal to XTAL1. This is due to the design of the oscillator, which has a auto-adapta-

tion gain control dedicated to external crystal.

If an external clock signal is directly provided on XTAL1 pin, then leave XTAL2 pin disconnected to

achieve the lowest consumption of the on-chip oscillator.

4 - ERRATA SHEET VERSION INFORMATION

This document was released in September 2003. It reflects the current silicon status of the

ST10F269Zxxx-D.

Name of the

Modification

Short Description

Fixed in Step

ST_PORT.2

Wrong Port Direction after Return From Power Down Mode

Name

Short Description

PWRDN.1

Execution of PWRDN Instruction

MAC.9

CoCMP Instruction Inverted Operands

MAC.10

E Flag Evaluation for CoSHR and CoASHR Instructions when Saturation Mode is Enabled

ST_PORT.3

Bad Behavior of Hysteresis Function on Input Falling Edge

Vih

Vil

“0”

PROBLEM

Input signal

(falling edge)

“1”

Internal

signal

(t2 - t1) > 1/Fcpu

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