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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F269ZX датащи(PDF) 181 Page - STMicroelectronics |
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ST10F269ZX датащи(HTML) 181 Page - STMicroelectronics |
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181 / 184 page  181/184 September 2003 1 - DESCRIPTION This Errata sheet describes the functional and electrical problems known in the D revision of the ST10F269Zxxx. The revision number can be found in the third line on the ST10F269 package. It looks like: ’xxxxxxxxx D’ where "D" identifies the revision number. 2 - FUNCTIONAL PROBLEMS The following malfunctions are known in this step: 2.1 - PWRDN.1 - Execution of PWRDN Instruction When instruction PWRDN is executed while pin NMI is at a high level (if PWRDCFG bit is clear in SYSCON register) or while at least one of the port 2 pins used to exit from power-down mode (if PWRD- CFG bit is set in SYSCON register) is at the active level, power down mode is not entered, and the PWRDN instruction is ignored. However, under the conditions described below, the PWRDN instruction is not ignored, and no further instructions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This problem only occurs in the following situations: a) The instructions following the PWRDN instruction are located in an external memory, and a multi- plexed bus configuration with memory tristate waitstate (bit MT-TCx = 0) is used. Or b) The instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral (XRAM,CAN), and the instructions following the PWRDN instruction are located in external memory. In this case, the problem occurs for any bus configuration. Note: The on-chip peripherals are still working correctly, in particular the Watchdog Timer, if not disabled, resets the device upon an overflow. Interrupts and PEC transfers, however, cannot be processed. In case NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered. No problem occurs if the NMI pin is low (if PWRDCFG = 0) or if all P2 pins used to exit from power-down mode are at inactive level (if PWRDCFG = 1): the chip normally enters powerdown mode. Workaround: Ensure that no instruction that writes to external memory or an XPeripheral preceeds the PWRDN instruction, otherwise insert a NOP instruction in front of PWRDN. When a multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM. ERRATA SHEET ST10F269Zxxx-D LIMITATIONS AND CORRECTIONS |
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