ST10F269ZX datasheet(176/184 Pages) STMICROELECTRONICS

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ST10F269

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The formula for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.

VCC = 5V ±10%, VSS = 0V, CPU clock = 32MHz, TA = -40 to +125°C, CL = 50pF (TQFP144 devices)

The formula for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer

t317 SR Read data setup time before latch

edge,

phase

error

detection

off

(SSCPEN = 0)

6–

–

t318 SR Read data hold time after latch edge,

phase

error

detection

off

(SSCPEN = 0)

–

2TCL + 6

–

Symbol

Parameter

Maximum Baud rate=10MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh)

Unit

Minimum

Maximum

Minimum

Maximum

Symbol

Parameter

Maximum Baud rate=6.25MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh)

Unit

Minimum

Maximum

Minimum

Maximum

t310 SR SSC clock cycle time

125

–

8 TCL

262144 TCL

t311 SR SSC clock high time

52.5

–

t310/2 - 10

–ns

t312 SR SSC clock low time

52.5

–

t310/2 - 10

–ns

t313 SR SSC clock rise time

–

t314 SR SSC clock fall time

–

t315 CC Write data valid after shift edge

–

45.25

–

2 TCL + 14

t316 CC Write data hold after shift edge

–

t317p SR Read data setup time before latch edge,

phase error detection on (SSCPEN = 1)

78.125

–

4TCL +

15.625

–ns

t318p

SR Read data hold time after latch edge,

phase error detection on (SSCPEN = 1)

109.375

–

6TCL +

15.625

–ns

t317 SR Read data setup time before latch edge,

phase error detection off (SSCPEN = 0)

6–

–

t318 SR Read data hold time after latch edge,

phase error detection off (SSCPEN = 0)

41.25

–

2TCL + 10

–

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