PM5356 datasheet(71/307 Pages) PMC

71 / 307 page

RELEASED

S/UNI-622-MAX

PMC-Sierra, Inc.

PM5356

S/UNI-622-MAX

DATASHEET

PMC-1980589

ISSUE 6

SATURN USER NETWORK INTERFACE (622-MAX)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

10.12 ATM UTOPIA System Interfaces

The S/UNI-622-MAX system interface can be configured for ATM cell data. The

system interface provides either a UTOPIA level 2 compliant bus or a UTOPIA

Level 3 compatible bus to allow the transfer of ATM cells between the ATM layer

device and the S/UNI-622-MAX.

10.12.1

Receive ATM Interface

The Receive ATM FIFO (RXCP) provides FIFO management at the S/UNI-622-

MAX receive cell interface. The receive FIFO contains four cells. The FIFO

provides the cell rate decoupling function between the transmission system

physical layer and the ATM layer.

In general, the management functions include filling the receive FIFO, indicating

when the receive FIFO contains cells, maintaining the receive FIFO read and

write pointers, and detecting FIFO overrun and underrun conditions.

UTOPIA Level 2 Interface

The UTOPIA Level 2 compliant interface accepts a read clock (RFCLK) and read

enable signal (RENB). The interface indicates the start of a cell (RSOC) and the

receive cell available status (RCA) when data is read from the receive FIFO

(using the rising edges of RFCLK). The RCA status changes from available to

unavailable when the FIFO is either empty (when RCALEVEL0 is high) or near

empty (when RCALEVEL0 is low). This interface also indicates FIFO overruns

via a maskable interrupt and register bits. Read accesses while RCA is a logic

zero will output invalid data. The FIFO is reset on FIFO overrun, causing up to 4

cells to be lost.

UTOPIA Level 3 Interface

The UTOPIA Level 3 compliant interface accepts a read clock (RFCLK) and read

enable signal (RENB). The interface indicates the start of a cell (RSOC) when

data is read from the receive FIFO (using the rising edges of RFCLK). The RVAL

signal indicates when data on the receive data bus RDAT[7:0] is valid. The

RPRTY signal reports the parity on the RDAT[7:0] bus (selectable as odd or even

parity). RVAL will not assert until RENB is asserted. This interface also indicates

FIFO overruns via a maskable interrupt and register bits. Read accesses while

RVAL is low are ignored and will output invalid data. The FIFO is reset on FIFO

overrun, causing up to 4 cells to be lost.

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