CY7C1069AV33
Document #: 38-05255 Rev. *F
Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°C to +150°C
Ambient Temperature with
Power Applied............................................. –55
°C to +125°C
Supply Voltage on VCC to Relative GND
[3] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
3.3V
± 0.3V
Industrial
–40
°C to +85°C
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
–10
–12
Unit
Min.
Max.
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
2.4
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
0.4
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[3]
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage Current GND < VOUT < VCC, Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
275
260
mA
ISB1
Automatic CE
Power-down Current
—TTL Inputs
CE2 < VIL,
Max. VCC, CE1 > VIH
VIN > VIH or VIN < VIL, f = fMAX
70
70
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 < 0.3V, Max. VCC,
CE1> VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
50
50
mA
Capacitance[4]
Parameter
Description
Test Conditions
TSOP II
FBGA
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
pF
COUT
I/O Capacitance
8
10
pF
AC Test Loads and Waveforms[5]
Notes:
3. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
90%
10%
3.3V
GND
90%
10%
All input pulses
3.3V
OUTPUT
5 pF*
*Including
jig and
scope
(a)
(b)
R1 317
Ω
R2
351
Ω
Rise time > 1V/ns
Fall time: > 1V/ns
(c)
OUTPUT
50
Ω
Z0= 50Ω
VTH = 1.5V
30 pF* *Capacitive Load consists of all
components of the test environment
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