CY7C1069AV33
Document #: 38-05255 Rev. *F
Page 4 of 9
AC Switching Characteristics Over the Operating Range [7]
Parameter
Description
–10
–12
Unit
Min.
Max.
Min.
Max.
Read Cycle
tpower
VCC(typical) to the First Access
[8]
11
ms
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
10
12
ns
tOHA
Data Hold from Address Change
3
3
ns
tACE
CE1 LOW/CE2 HIGH to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
6
ns
tLZOE
OE LOW to Low-Z
[9]
11
ns
tHZOE
OE HIGH to High-Z[
9]
56
ns
tLZCE
CE1 LOW/CE2 HIGH to Low-Z
[9]
33
ns
tHZCE
CE1 HIGH/CE2 LOW to High-Z
[9]
56
ns
tPU
CE1 LOW/CE2 HIGH to Power-up
[10]
00
ns
tPD
CE1 HIGH/CE2 LOW to Power-down
[10]
10
12
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
10
12
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
7
8
ns
tAW
Address Set-up to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-up to Write End
5.5
6
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low-Z
[9]
33
ns
tHZWE
WE LOW to High-Z[
9]
56
ns
Data Retention Waveform
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is
started.
9. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
3.0V
3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
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