P4C164

Page 7 of 16

Document # SRAM115 REV F

Mode

CE

CE

CE

CE

CE

1

CE

2

OE

OE

OE

OE

OE

WE

WE

WE

WE

WE

I/O

Power

Standby

H

X

X

X

High Z

Standby

Standby

X

L

X

X

High Z

Standby

D

OUT

Disabled

L

H

H

H

High Z

Active

Read

L

H

L

H

D

OUT

Active

Write

L

H

X

L

High Z

Active

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

TRUTH TABLE

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Because of the high speed of the P4C164/L, care must be taken when

testing this device; an inadequate setup can cause a normal functioning

part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V

directly up to the contactor fingers. A 0.01 µF high frequency capacitor

is also required between V

To avoid signal reflections,

proper termination must be used; for example, a 50

Ω test environment

should be terminated into a 50

Ω load with 1.73V (Thevenin Voltage) at

the comparator input, and a 116

Ω resistor must be used in series with

D

LCC (L5)

"LS" - SPECIAL PIN-OUT

LCC PIN CONFIGURATIONS

LCC (L6)

LCC (L5)

"L" - STANDARD PIN-OUT