P4C164

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Document # SRAM115 REV F

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

(V

(2)

Notes:

5.

WE is HIGH for READ cycle.

6.

CE

7. ADDRESS must be valid prior to, or coincident with

CE

LOW and CE

8. Transition is measured ± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is

sampled and not 100% tested.

TIMING WAVEFORM OF READ CYCLE NO. 1 (

OE

OE

OE

OE

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Read Cycle

Time

8

1012152025

35

4570

100

ns

Address

Access Time

8

10

12

152025354570

100

ns

Chip Enable

Access Time

8

10

12

152025354570

100

ns

Output Hold

from Address

Change

333333333

3

ns

Chip Enable to

Output in Low Z

222222222

2

ns

Chip Disable

to Output in

High Z

5678

8

10

15

20

35

45

ns

Output Enable

Low to Data

Valid

5679

10

13

18

20

35

45

ns

Output Enable

Low to Low Z

222222222

2

ns

Output Enable

High to High Z

5679

9

12

15

20

35

45

ns

Chip Enable to

Power Up

Time

000000000

0

ns

Chip Disable

to Power Down

Time

8

10

12

15202020253545

ns

Symbol

Parameter

-8

-10

-12

-15

-20

-25

Unit

-35

-45

-70

-100