PCA9641PW datasheet(16/55 Pages) NXP

16 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

16 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

8.3 Register 2: Status register ([B2:B0] = 010b)

Table 10.

STATUS - Status register (pointer address 02h) bit description

POR = 00h.

Legend: * default value

Bit

Symbol

Access

Value

Description

SDA_IO

R/W

SDA becomes I/O pin; master can read or write to

this register bit. If master reads this bit, the value is

the state of the downstream SDA pin. Zero value

means SDA is LOW, and one means SDA pin is

HIGH.

When master writes ‘0’ to this register bit, the

downstream SDA pin will assert LOW.

If master writes ‘1’ to this register bit, the

downstream SDA pin will be pulled HIGH.

Remark: SDA becomes I/O pin only when

BUS_CONNECT = 0 and LOCK_GRANT = 1.

When read, indicates the SDA pin of the

downstream bus is LOW.

When written, PCA9641 drives SDA pin of

downstream bus LOW.

When read, indicates the SDA pin of the

downstream bus is HIGH.

When written, PCA9641 drives SDA pin of the

downstream bus HIGH.

SCL_IO

R/W

SCL becomes I/O pin; master can read or write to

this register bit. If master reads this bit, the value is

the state of the downstream SCL pin. Zero value

means SCL is LOW, and one means SCL pin is

HIGH.

When master writes ‘0’ to this register bit, the

downstream SCL pin will assert LOW.

If master writes ‘1’ to this register bit, the

downstream SCL pin will be pulled HIGH.

Remark: SCL becomes I/O pin only when

BUS_CONNECT = 0 and LOCK_GRANT = 1.

When read, shows the SCL pin of the downstream

bus is LOW.

When written, PCA9641 drives SCL pin of

downstream bus LOW.

When read, shows the SCL pin of the downstream

bus is HIGH.

When written, PCA9641 drives SCL pin of the

downstream bus HIGH.

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