PM5313 datasheet(83/646 Pages) PMC

83 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

TLD

Input

C23

The transmit line DCC (TLD) bit serial input signal

contains the line data communication channel (D4-

D12) to be transmitted.

TLD is sampled on the rising edge of TLDCLK. The

TTOH and TTOHEN inputs take precedence over

TLD.

The TTOC Overhead Control register contains the

TX_GAPSEL register bit used to select the smooth

or gapped TLDCLK output clock and the TLD_TS

output.

TOWCLK

Output

A24

The transmit order wire clock (TOWCLK) is used to

clock in transmit section orderwire, user channel

and line orderwire. (TSOW, TSUC and TLOW). A

smooth or gapped version of this clock may be

selected.

When selecting the smooth clock, TOWCLK is a 64

kHz clock with nominal 50% duty cycle.

When selecting the gapped clock, TOWCLK is a 64

kHz clock generated by gapping a 72 kHz clock.

In all cases, TSOW, TSUC and TLOW are sampled

on the rising edge of TOWCLK. In gapped clock

mode, a gap detector on TOWCLK is needed to

identify the MSB on TSOW, TSUC and TLOW. An

edge detection on TFP may also be used. In

smooth clock mode, TTOHFP may be used to

identify the rising edge when the MSB should be

present on TSOW, TSUC and TLOW.

The TTOC Overhead Control register contains the

TX_GAPSEL register bit used to select the smooth

or gapped TOWCLK output clock.

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