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PM5313 датащи(PDF) 61 Page - PMC-Sierra, Inc

номер детали PM5313
подробное описание детали  SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S
PDF  646 Pages
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производитель  PMC [PMC-Sierra, Inc]
домашняя страница  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5313 датащи(HTML) 61 Page - PMC-Sierra, Inc

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PRODUCTION
PMC-Sierra, Inc.
PM5313 SPECTRA-622
DATASHEET
PMC-1981162
ISSUE 6
SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S
PROPRIETARY AND CONFIDENTIAL
29
Pin Name
Type
Pin
No.
Function
TPL
Output
AK7
The transmit payload output (TPL) is an active high
signal that indicates when the transmit data bus
TD[7:0] is carrying a payload byte. It is set high
during path overhead and payload bytes and low
during transport overhead bytes. TPL is set high
during the H3 byte to indicate a negative pointer
justification event and set low during the byte
following H3 to indicate a positive pointer
justification event.
TPL is updated on the rising edge of TCLK.
TC1J1V1/
Output
AJ8
The transmit composite timing signal (TC1J1V1)
indicates the frame, payload and tributary
multiframe boundaries on the transmit data bus
TD[7:0] when the TC1J1V1EN bit in the SPECTRA-
622 Transmit Telecom Bus Configuration register is
set high. TC1J1V1 pulses high with the transmit
payload active signal (TPL) set low to mark the first
STS-1 (STM-0/AU3) identification byte (C1).
TC1J1V1 pulses high with TPL set high to mark the
path trace byte(s) (J1). Optionally, the TC1J1V1
signal pulses high on the V1 byte(s) to indicate
tributary multiframe boundaries.
TC1J1V1 is updated on the rising edge of TCLK.
TFPO
Output
The transmit frame pulse output (TFPO) is an
active-high signal marking the frame alignment on
the serial stream TXD+/- or parallel transmit data
TD[7:0] when the TC1J1V1EN bit in the SPECTRA-
622 Transmit Telecom Bus Configuration register is
set low. In parallel mode, TFPO is set high for a
single TCLK period during the first SPE
(synchronous payload envelope) byte after the
J0/Z0 bytes on TD[7:0]. In serial mode, it will rising
15 bits (+/- 3 bits) before the first byte of the SPE
on TXD.
TFPO is updated on the rising edge of TCLK.



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