ADS1626IPAPR datasheet(24/37 Pages) TI

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ADS1625

ADS1626

SBAS280E − JUNE 2003 − REVISED MAY 2007

www.ti.com

FIFO (ADS1626 ONLY)

The ADS1626 includes an adjustable level first-in first-out

buffer (FIFO) for the output data. The FIFO allows data to

be temporarily stored within the ADS1626 to provide more

flexibility for the host controller when retrieving data. Pins

FIFO_LEV[2:0] set the level or depth of the FIFO. Note that

these pins must be left unconnected on the ADS1625. The

FIFO is enabled by setting at least one of the FIFO_LEV

inputs high. Table 5 shows the corresponding FIFO level

and DRDY period for the different combinations of

FIFO_LEV[2:0] settings. For the best performance when

using the FIFO, it is recommended to:

Set IOVDD = 3V.

Synchronize data retrieval with CLK.

Minimize loading on outputs DOUT[17:0].

Ensure rise and fall times on CLK and RD are 1ns or

longer.

Table 5. FIFO Buffer Level Settings for the

ADS1626

FIFO_LEV[2:0]

FIFO BUFFER LEVEL

DRDY PERIOD

000

0: disabled,

operates like ADS1625

32/fCLK

001

64/fCLK

010

128/fCLK

011

192/fCLK

100

256/fCLK

101

320/fCLK

110

384/fCLK

111

448/fCLK

FIFO Operation

The ADS1626 FIFO collects the number of output

readings

set

the

level

corresponding

the

FIFO_LEV[2:0] setting. When the specified level is

reached, DRDY is pulsed high, indicating the data in the

FIFO are ready to be read. The DRDY period is a function

of the FIFO level, as shown in Table 5. To read the data,

make sure CS is low (it is acceptable to tie it low) and then

take RD low. The first, or oldest, data will be presented on

the data output pins. After reading this data, advance to the

next data reading by toggling RD. On the next falling edge

of RD, the second data are present on the data output pins.

Continue this way until all the data have been read from the

FIFO, making sure to take RD high when complete.

Afterwards, wait until DRDY toggles and repeat the

readback cycle. Figure 23 shows an example readback

when FIFO_LEV[2:0] = 010 (level = 4).

Readback considerations

The exact number of data readings set by the FIFO level

must be read back each time DRDY toggles. The one

exception is that readback can be skipped entirely. In this

case, the DRDY period increases to 512 CLK period.

Figure 24 illustrates an example when readback is

skipped with the FIFO level = 4. Do not read back more or

less readings from the FIFO than set by the level. This

interrupts the FIFO operation and can cause DRDY to stay

low indefinitely. If this occurs, the RESET pin must be

toggled followed by a RD pulse. This resets the ADS1626

FIFO and also the digital filter, which must settle

afterwards before valid data is ready. See the section,

Resetting the ADS1626, for more details. Also note that

the RD signal is independent of the CS signal. Therefore,

when multiple devices are used, the RD signal should not

be shared. Alternatively, individual RD signals can be

generated by performing an OR operation with the CS

signal.

Setting the FIFO Level

The FIFO level setting is usually a static selection that is

set when power is first applied to the ADS1626. If the FIFO

level needs to be changed after powerup, there are two

options. One is to asynchronously set the new value on pin

FIFO_LEV[2:0] then toggle RESET. Remember that the

ADS1626 will need to settle after resetting. See the

section, Resetting the ADS1626, for more details. The

other option avoids requiring a reset, but needs

synchronization of the FIFO level change with the

readback. The FIFO_LEV[2:0] pins have to be changed

after RD goes high after reading the first data, but before

RD goes low to read the last data from the FIFO. The new

FIFO level becomes active immediately and the DRDY

period adjusts accordingly. When decreasing the FIFO

level this way, make sure to give adequate time for

readback of the data before setting the new, smaller level.

Figure 25 illustrates an example of a synchronized FIFO

level change from 4 to 8.

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