ADS1626IPAPR datasheet(20/37 Pages) TI

20 / 37 page

ADS1625

ADS1626

SBAS280E − JUNE 2003 − REVISED MAY 2007

www.ti.com

CLOCK INPUT (CLK)

The ADS1625/6 requires an external clock signal to be

applied to the CLK input pin. The sampling of the

modulator is controlled by this clock signal. As with any

high-speed data converter, a high quality clock is essential

for optimum performance. Crystal clock oscillators are the

recommended CLK source; other sources, such as

frequency synthesizers, are usually not adequate. Make

sure to avoid excess ringing on the CLK input; keeping the

trace as short as possible will help.

Measuring

high-frequency,

large-amplitude

signals

requires tight control of clock jitter. The uncertainty during

sampling of the input from clock jitter limits the maximum

achievable SNR. This effect becomes more pronounced

with higher frequency and larger magnitude inputs.

Fortunately,

the

ADS1625/6

oversampling topology

reduces clock jitter sensitivity over that of Nyquist rate

converters like pipeline and successive approximation

converters by a factor of

√32.

In order to not limit the ADS1625/6 SNR performance,

keep the jitter on the clock source below the values shown

in Table 1. When measuring lower frequency and lower

amplitude inputs, more CLK jitter can be tolerated. In

determining the allowable clock source jitter, select the

worst-case input (highest frequency, largest amplitude)

that will be seen in the application.

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

INPUT SIGNAL

MAXIMUM

ALLOWABLE

MAXIMUM

FREQUENCY

MAXIMUM

AMPLITUDE

ALLOWABLE

CLOCK SOURCE

JITTER (RMS)

500kHz

−2dB

7ps

500kHz

−20dB

50ps

100kHz

−2dB

35ps

100kHz

−20dB

285ps

DATA FORMAT

The 18-bit output data is in binary two’s complement format,

as shown in Table 2. Under normal operation, the output

codes range between 200A8h to 1FF57h. Signals less than

−1.467VREF will clip at 200A8h and likewise, signals greater

than 1.467VREF will clip at 1FF57h. For large step changes

on the inputs, the output clips at the positive full-scale value

of 1FFFFh (positive transients) or the negative full-scale

value of 20000h (negative transients).

Table 2. Output Code Versus Input Signal

INPUT SIGNAL

(INP – INN)

IDEAL OUTPUT

CODE(1)

OTR

≥ +1.467VREF (> 0dB)(2)

1FFFFh

≥ +1.467VREF (0dB)

1FF57h

+1.467V

REF

217

* 1

00001h

00000h

−1.467V

REF

217

* 1

3FFFFh

v −1.467V

REF

217

* 1

200A8h

v −1.467V

REF

217

* 1

(2)

20000h

(1) Excludes effects of noise, INL, offset and gain errors.

(2) Large step inputs.

OUT-OF-RANGE INDICATION (OTR)

If the output code on DOUT[17:0] exceeds the positive or

negative full-scale, the out-of-range digital output OTR will

go high on the falling edge of DRDY. When the output code

returns within the full-scale range, OTR returns low on the

falling edge of DRDY.

DATA RETRIEVAL

Data retrieval is controlled through a simple parallel

interface. The falling edge of the DRDY output indicates

new data are available. To activate the output bus, both CS

and RD must be low, as shown in Table 3. On the

ADS1625, both of these signals can be tied low. On the

ADS1626 with FIFO enabled, only CS can be tied low

because RD must toggle to operate the FIFO. See the

FIFO section for more details. Make sure the DOUT bus

does not drive heavy loads (> 20pF), as this will degrade

performance. Use an external buffer when driving an edge

connector or cables.

Table 3. Truth Table for CS and RD

DOUT[17:0]

Active

High impedance

ADS1626IPAPR датащи(PDF) 20 Page - Texas Instruments

ADS1626IPAPR датащи(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

датащи скачать

ссылки URL