PM3351-SW datasheet(13/268 Pages) PMC

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PM3351 ELAN 1X100

DATA SHEET

PMC-970113

ISSUE 3

SINGLE PORT FAST ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Expansion Port

A 32-bit parity-checked PCI-based expansion port is provided to allow the ELAN 1x100

to communicate transparently with other PCI bus devices to implement switches that

have multiple 100Mbit/s and 10Mbit/s ports. The expansion port supports a maximum

throughput of over 1 Gbit/s, and requires only a single PAL or similar device serving as

a bus arbiter. A common protocol is used for inter-chip communication between the

ELAN 1x100 (PM3351) and ELAN 8x10 (PM3350). Packets received on an ELAN

1x100 MAC port that are destined for an external ELAN switch chip are transferred over

the expansion bus prior to transmission on the designated destination port. Broadcast

and multicast packets are handled using a two-level replication scheme, in which the

broadcast/multicast frame is first transferred to all of the external ELAN switch chips,

after which it is transmitted out the required destination ports without any further use of

the expansion bus. (In the case of an ELAN 1x100, only one port is present in each

destination device, and hence only one level of replication takes place.) In addition,

ELAN switch chips interconnected via the PCI bus exchange information to maintain the

distributed MIB.

The expansion port is compatible with the industry-standard Peripheral Component

Interconnect (PCI) specification version 2.1, which allows the ELAN 1x100 chip to be

directly interfaced to any host computer supporting the PCI bus. The host CPU can

then communicate with the ELAN 1x100 and control its functions, greatly expanding the

range of potential applications. The maximum PCI clock of 40 MHz is supported.

Local Memory Controller

The local memory is used for holding configuration information, MAC address tables

and statistics tables, node management data, packet buffers, and host communication

queues if a local host CPU is present. The ELAN 1x100 integrates a memory controller

that is capable of addressing and directly driving up to 16 MBytes of external memory,

divided into four banks of 4 MBytes each, with decoded selects for each bank.1

Independent, software programmable access times may be set for each bank, allowing

a glueless interface to a mix of SRAM, , EEPROM, and EPROM in the same system.

An external memory timing generator may also be used if desired. The memory

controller accepts simultaneous requests from the Switch Processor, the DMA

processor, and the expansion port, and efficiently partitions the 100 MByte-per-second

memory port bandwidth among them.

The ELAN 1x100 is capable of auto-configuring after power-up via an 8-bit EPROM or

EEPROM connected to the memory port. Parameters (such as the MAC address, IP

1 When accessing SRAM and EEPROM devices, however, the actual limit is 1 Mbyte per bank, as the

upper bits of the internal address bus are not brought out to physical pins. The entire 4 Mbytes per bank is

only accessible when using DRAM memory types.

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