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PM3351-SW датащи(PDF) 39 Page - PMC-Sierra, Inc |
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PM3351-SW датащи(HTML) 39 Page - PMC-Sierra, Inc |
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39 / 268 page ![]() PM3351 ELAN 1X100 DATA SHEET PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 33 FUNCTIONAL DESCRIPTION Overview This section will provide an overview of the PM3351 ELAN 1x100 components, the device initialization and configuration process, the structures built and used by the device to perform its functions, and a brief description of how packets are switched by the device. System Components In order to describe the functions and operation of the ELAN 1x100 device, it is first necessary to discuss the operating environment that is intended to be built around it. A typical simple switching subsystem utilizing the ELAN 1x100 device consists of: 1. The ELAN 1x100 device itself. (Clearly, a complete system will include more than a single ELAN 1x100 device, but this is not shown in the diagram below.) 2. A set of SRAM devices that provide the operating memory for the ELAN 1x100. This memory should be mapped to the lowest bank of the ELAN 1x100 address space (i.e., addresses starting at 0x000000 hex). The amount of SRAM provided is a system-dependent parameter; a minimum system with about 150 kB of buffer space and around 1200 MAC addresses in the address table requires 512kB of SRAM. SRAM requirements for this and other system configurations may be computed using parameters supplied later in this document. 3. An EPROM containing the bootstrap image for the ELAN 1x100 (i.e., the operating firmware, operating parameters, and system initialization code) if this ELAN device is designated as the system master. This EPROM is mapped to the second lowest bank of the ELAN 1x100 memory address space (the 4 MB address range starting at address 0x400000 hex.) The size of the EPROM is highly dependent on the operating configuration of the ELAN 1x100, with the minimum requirement being 32 kB. 4. External transceiver devices that implement the PHY layer functions required for 100BaseT Ethernet. 5. An LED register, connected to a bank of eight LEDs, that may be used to report status information for diagnostic purposes if required. The LED register is mapped into the third bank of ELAN 1x100 memory address space, starting at 0x800000 hex. 6. A system voltage monitor or other means of asserting a system reset for a specified time after the power supply voltage has stabilized, plus, if desired, a pushbutton switch for forcing a system reset after power-up. |
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