CS5101A datasheet(22/39 Pages) CIRRUS

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CS5101A CS5102A

DS45F6

5. SYSTEM DESIGN USING THE CS5101A & CS5102A

Figure 9 shows a general system connection diagram for the CS5101A and CS5102A.

Figure 9. CS5101A/CS5102A System Connection Diagram

5.1

System Initialization

Upon power up, the CS5101A and CS5102A must

be reset to guarantee a consistent starting condi-

tion and to initially calibrate the device. Due to

each device's low power dissipation and low tem-

perature drift, no warm-up time is required before

reset to accommodate any self-heating effects.

However, the voltage reference input should have

stabilized to within 0.25% of its final value before

RST rises to guarantee an accurate calibration.

Later, the CS5101A and CS5102A may be reset at

any time to initiate a single full calibration.

When RST is brought low all internal logic clears.

When RST returns high on the CS5101A, a cali-

bration cycle begins which takes 11,528,160 mas-

ter clock cycles to complete (approximately

1.4 seconds with an 8 MHz master clock). The cal-

ibration cycle on the CS5102A takes 2,882,040

master clock cycles to complete (approximately

1.8 seconds with a 1.6 MHz master clock). The

CS5101A's and CS5102A's STBY output remains

low throughout the calibration sequence, and a ris-

ing transition indicates the device is ready for nor-

mal operation. While calibrating, the CS5101A and

CS5102A will ignore changes on the HOLD input.

To perform the reset function, a simple power-on

reset circuit can be built using a resistor and ca-

pacitor as shown in Figure 10. The resistor should

be less than or equal to 10 k

Ω. The system power

supplies, voltage reference, and clock should all be

established prior RST rising.

VA+

VD +

+5 V A

4.7

µF

0.1

µF

0.1

µF

-5 V A

4.7

µF

0.1

µF1 µF

0.1

µF

0.1

µF

VA-

VD -

REF B UF

CL KIN

XO UT

DG N D

SLEEP

STBY

TR K 1

TR K 2

SS H /S D L

SDA T A

RST

CH1 /2

SC L K

HOL D

10 M

EXT

CL O C K

C2 = C 1

Da ta

In te rfa ce

Co n tro l

Lo gic

CR S/FIN

COD E

SC K M O D

OU T M OD

BP /U P

VD+

Mo d e C o n tro l

AIN 1

AIN 2

1 nF

An a lo g

So u rce s

VRE F

AG ND

V o ltage R e fe rence

* F o r be st d y nam ic

S /(N + D ) pe rform a n c e.

NP O

U n used L ogic in p u ts sh ou ld

b e tie d to V D + o r D G N D .

C S5101A

C S5102A

XTAL

XTAL & C1 T ab le

C S 5101 A

FR N

C S 5102 A

FR N

XTAL

8.0 M H z

8.19 2 M H z

1.6 M H z

C1 , C 2

10 pF

30 pF

2.0 M H z

1.6 M H z

TST

PD T, R B T ,

SSC

PD T, R B T ,

SSC

C0G

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