MP86950

– INTELLI-PHASETM SOLUTION

W/ INTEGRATED MOSFETS AND DRIVERS

MP86950 Rev. 1.0

www.MonolithicPower.com

12

12/18/2020

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APPLICATION INFORMATION

PCB Layout Guidelines

Efficient layout is critical for stable operation.

For the best results, refer to Figure 3 and follow

the guidelines below:

1. Place the MLCC input capacitors as close to

VIN and PGND as possible.

2. Place

as

many

VIN

and

PGND

vias

underneath the package as possible. Place

these vias between the VIN or PGND long

pads.

3. Place a VIN copper plane on the second

inner

layer

to

form

the

PCB

stack

(positive/negative/positive)

to

reduce

parasitic impedance from the MLCC input

capacitor to the MP86950. Ensure that the

copper plane on the inner layer covers the

VIN vias and MLCC input capacitors.

4. Place more PGND vias close to the PGND

pin/pad to minimize parasitic resistance,

parasitic impedance, and thermal resistance.

5. Place the BST capacitor, BST resistor, and

VDRV capacitor as close to the

MP86950’s

pins as possible. For BST routing, use a

trace width greater than 20mils. Avoid

placing vias on the BST driving path.

6. Place the VDD decoupling capacitor close

to the device.

7. Keep the CS signal trace away from high

voltages and current slew-rate nodes (such

as SW, PWM, the VIN vias, and the PGND

vias).

Figure 3: Recommended PCB Layout

Input Capacitor: 0402 Package (Top Side) and 0805 Package (Bottom Sides)

BST/VDRV/VDD Capacitor/Resistor: 0402 Package

Via Size: 10/20mils