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PACE1750AE

Document # MICRO-2 REV G

Notes

1. 4.5V

2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in

parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced.

When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high

impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.

Min

Max

Min

Max

Min

Max

25

25

20

ns

SNEW

26

25

22

ns

TRIGO RST

26

25

22

ns

35

35

30

ns

DMA enable

35

35

30

ns

Normal power up

35

35

30

ns

Clock to major error unrecoverable

50

50

45

ns

RESET

40

40

30

ns

Console request

00

0

ns

Console request

10

10

10

ns

Level sensitive faults

55

5

ns

Level sensitive faults

55

5

ns

00

0

ns

Power down interrupt level sensitive

hold

10

10

10

ns

20

20

15

ns

Clock to three-state

17

17

13

ns

Edge sensitiive pulse width

55

5

ns

Clock rise and fall

55

5

ns

40 MHz

Unit

SIGNAL PROPAGATION DELAYS

Symbol

Parameter

20 MHz

30 MHz