PIC16F690-ESLASHSS datasheet(71/294 Pages) MICROCHIP

71 / 294 page

DS41262D-page 69

PIC16F631/677/685/687/689/690

4.3

PORTB and TRISB Registers

PORTB is a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB (Register

4-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 4-3 shows how to initialize PORTB. Reading

the PORTB register (Register 4-5) reads the status of the

pins, whereas writing to it will write to the PORT latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified and then written to the PORT

data latch.

The TRISB register controls the PORTB pin output

drivers, even when they are being used as analog inputs.

The user should ensure the bits in the TRISB register are

maintained set when using them as analog inputs. I/O

pins configured as analog input always read ‘0’.

EXAMPLE 4-3:

INITIALIZING PORTB

4.4

Additional PORTB Pin Functions

PORTB pins RB<7:4> on the device family device have

an interrupt-on-change option and a weak pull-up

option. The following three sections describe these

PORTB pin functions.

4.4.1

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:4> enable or

disable each pull-up (see Register 4-9). Each weak

pull up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the RABPU bit of the OPTION

4.4.2

INTERRUPT-ON-CHANGE

Four of the PORTB pins are individually configurable as

an interrupt-on-change pin. Control bits IOCB<7:4>

enable or disable the interrupt function for each pin.

Refer to Register 4-10. The interrupt-on-change feature

is disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the present

value is compared with the old value latched on the last

read of PORTB to determine which bits have changed

or mismatch the old value. The ‘mismatch’ outputs are

OR’d together to set the PORTB Change Interrupt flag

bit (RABIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the interrupt by:

Any read or write of PORTB. This will end the

mismatch condition.

Clear the flag bit RABIF.

A mismatch condition will continue to set flag bit RABIF.

Reading or writing PORTB will end the mismatch

condition and allow flag bit RABIF to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After these Resets, the RABIF flag will

continue to be set if a mismatch is present.

Note:

The ANSELH register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

BCF

STATUS,RP0 ;Bank 0

BCF

STATUS,RP1 ;

CLRF

PORTB

;Init PORTB

BSF

STATUS,RP0 ;Bank 1

MOVLW

FFh

;Set RB<7:4> as inputs

MOVWF

TRISB

;

BCF

STATUS,RP0 ;Bank 0

Note:

If a change on the I/O pin should occur when

the read operation is being executed (start of

the Q2 cycle), then the RABIF interrupt flag

may not get set. Furthermore, since a read

or write on a port affects all bits of that port,

care must be taken when using multiple pins

in Interrupt-on-Change mode. Changes on

one pin may not be seen while servicing

changes on another pin.

PORTB: PORTB REGISTER

R/W-x

U-0

RB7

RB6

RB5

RB4

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

RB<7:4>: PORTB I/O Pin bit

= Port pin is > VIH

= Port pin is < VIL

bit 3-0

Unimplemented: Read as ‘0’

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