DSPIC30F3012AT20ESLASHML datasheet(133/205 Pages) MICROCHIP

133 / 205 page

DS70139E-page 131

dsPIC30F2011/2012/3012/3013

17.8

Peripheral Module Disable (PMD)

Registers

The Peripheral Module Disable (PMD) registers pro-

vide a method to disable a peripheral module by stop-

ping all clock sources supplied to that module. When a

peripheral is disabled via the appropriate PMD control

bit, the peripheral is in a minimum power consumption

state. The Control and Status registers associated with

the peripheral will also be disabled so writes to those

registers will have no effect and read values will be

invalid.

A peripheral module will only be enabled if both the

associated bit in the the PMD register is cleared and

the peripheral is supported by the specific dsPIC DSC

variant. If the peripheral is present in the device, it is

enabled in the PMD register by default.

17.9

In-Circuit Debugger

When MPLAB® ICD2 is selected as a Debugger, the In-

Circuit Debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. When the device has this feature enabled,

some of the resources are not available for general

use. These resources include the first 80 bytes of Data

RAM and two I/O pins.

One of four pairs of Debug I/O pins may be selected by

the user using configuration options in MPLAB IDE.

These pin pairs are named EMUD/EMUC, EMUD1/

EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3.

In each case, the selected EMUD pin is the Emulation/

Debug Data line, and the EMUC pin is the Emulation/

Debug Clock line. These pins will interface to the

MPLAB ICD 2 module available from Microchip. The

selected pair of Debug I/O pins is used by MPLAB

ICD 2 to send commands and receive responses, as

well as to send and receive data. To use the In-Circuit

Debugger function of the device, the design must

implement ICSP connections to MCLR, VDD, VSS,

PGC, PGD and the selected EMUDx/EMUCx pin pair.

This gives rise to two possibilities:

If EMUD/EMUC is selected as the Debug I/O pin

pair, then only a 5-pin interface is required, as

the EMUD and EMUC pin functions are multi-

plexed with the PGD and PGC pin functions in

all dsPIC30F devices.

If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/

EMUC3 is selected as the Debug I/O pin pair,

then a 7-pin interface is required, as the

EMUDx/EMUCx pin functions (x = 1, 2 or 3) are

not multiplexed with the PGD and PGC pin

functions.

Note:

If a PMD bit is set, the corresponding mod-

ule is disabled after a delay of 1 instruction

cycle. Similarly, if a PMD bit is cleared, the

corresponding module is enabled after a

delay of 1 instruction cycle (assuming the

module Control registers are already

configured to enable module operation).

Note:

In the dsPIC30F2011, dsPIC30F3012 and

dsPIC30F2012 devices, the U2MD bit is

readable and writable and will be read as

‘1’ when set.

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