DSPIC30F3012AT20ESLASHML datasheet(131/205 Pages) MICROCHIP

131 / 205 page

DS70139E-page 129

dsPIC30F2011/2012/3012/3013

17.4

Watchdog Timer (WDT)

17.4.1

WATCHDOG TIMER OPERATION

The primary function of the Watchdog Timer (WDT) is

to reset the processor in the event of a software mal-

function. The WDT is a free-running timer which runs

off an on-chip RC oscillator, requiring no external com-

ponent. Therefore, the WDT timer will continue to oper-

ate even if the main processor clock (e.g., the crystal

oscillator) fails.

17.4.2

ENABLING AND DISABLING

THE WDT

The Watchdog Timer can be “Enabled” or “Disabled”

only through a Configuration bit (FWDTEN) in the

Configuration register, FWDT.

Setting FWDTEN = 1 enables the Watchdog Timer. The

enabling is done when programming the device. By

default, after chip erase, FWDTEN bit = 1. Any device

programmer

capable

programming

dsPIC30F

devices allows programming of this and other Configu-

ration bits.

If enabled, the WDT will increment until it overflows or

“times out”. A WDT time-out will force a device Reset

(except during Sleep). To prevent a WDT time-out, the

user must clear the Watchdog Timer using a CLRWDT

instruction.

If a WDT times out during Sleep, the device will wake-

up. The WDTO bit in the RCON register will be cleared

to indicate a wake-up resulting from a WDT time-out.

Setting FWDTEN = 0 allows user software to enable/

disable the Watchdog Timer via the SWDTEN

(RCON<5>) control bit.

17.5

Low Voltage Detect

The Low Voltage Detect (LVD) module is used to detect

when the VDD of the device drops below a threshold

value, VLVD, which is determined by the LVDL<3:0>

bits (RCON<11:8>) and is thus user programmable.

The internal voltage reference circuitry requires a nom-

inal amount of time to stabilize, and the BGST bit

(RCON<13>) indicates when the voltage reference has

stabilized.

In some devices, the LVD threshold voltage may be

applied externally on the LVDIN pin.

The LVD module is enabled by setting the LVDEN bit

(RCON<12>).

17.6

Power-Saving Modes

There are two power-saving states that can be entered

through the execution of a special instruction, PWRSAV;

these are Sleep and Idle.

The format of the PWRSAV instruction is as follows:

PWRSAV <parameter>

, where ‘parameter’ defines

Idle or Sleep mode.

17.6.1

SLEEP MODE

In Sleep mode, the clock to the CPU and peripherals is

shut down. If an on-chip oscillator is being used, it is

shut down.

The Fail-Safe Clock Monitor is not functional during

Sleep since there is no clock to monitor. However,

LPRC clock remains active if WDT is operational during

Sleep.

The brown-out protection circuit and the Low-Voltage

Detect circuit, if enabled, will remain functional during

Sleep.

The processor wakes up from Sleep if at least one of

the following conditions has occurred:

• any interrupt that is individually enabled and

meets the required priority level

• any Reset (POR, BOR and MCLR)

• WDT time-out

On waking up from Sleep mode, the processor will

restart the same clock that was active prior to entry into

Sleep mode. When clock switching is enabled, bits

COSC<2:0> will determine the oscillator source that

will be used on wake-up. If clock switch is disabled,

then there is only one system clock.

If the clock source is an oscillator, the clock to the

device will be held off until OST times out (indicating a

stable oscillator). If PLL is used, the system clock is

held off until LOCK = 1 (indicating that the PLL is

stable). In either case, TPOR, TLOCK and TPWRT delays

are applied.

If EC, FRC, LPRC or ERC oscillators are used, then a

delay of TPOR (~ 10

μs) is applied. This is the smallest

delay possible on wake-up from Sleep.

Moreover, if LP oscillator was active during Sleep and

LP is the oscillator used on wake-up, then the start-up

delay will be equal to TPOR. PWRT delay and OST

timer delay are not applied. In order to have the small-

est possible start-up delay when waking up from Sleep,

one of these faster wake-up options should be selected

before entering Sleep.

Note:

If a POR or BOR occurred, the selection of

the oscillator is based on the FOS<2:0>

and FPR<4:0> Configuration bits.

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