M24M02E-F datasheet(35/54 Pages) STMICROELECTRONICS

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Table 20. AC characteristics in Fast-mode Plus

Symbol

Alt.

Parameter

Min.

Max.

Unit

fSCL

Clock frequency

MHz

tCHCL

tHIGH

Clock pulse width high

260

tCLCH

tLOW

Clock pulse width low

500

tXH1XH2

Input signal rise time

(1)

tXL1XL2

Input signal fall time

(1)

tQL1QL2(2)

SDA (out) fall time

20(3)

120

tDXCH

tSU:DAT

Data in setup time

tCLDX

tHD:DAT

Data in hold time

tCLQX(4)

tDH

Data out hold time

100

tCLQV(5)

tAA

Clock low to next data valid (access time)

450

tCHDL

tSU:STA

Start condition setup time

250

tDLCL

tHD:STA

Start condition hold time

250

tCHDH

tSU:STO

Stop condition setup time

250

tDHDL

tBUF

Time between Stop condition and next Start condition

500

tWLDL(2)(6)

tSU:WC

WC set up time (before the start condition)

μs

tDHWH(2)(7)

tHD:WC

WC hold time (after the stop condition)

μs

tWR

Write cycle time

4(8)

tNS(2)

Pulse width ignored (input filter on SCL and SDA)

tWU(9)(10)

Wake up time

μs

1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification

that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.

2. Evaluated by characterization - Not tested in production.

3. With CL = 10 pF.

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of

SDA.

5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming

that the Rbus × Cbus time constant is within the values specified in Figure 26.

6. WC = 0 setup time condition to enable the execution of a write command.

7. WC = 0 hold time condition to enable the execution of a write command.

8. 3.3 ms typical.

9. Specified by design - Not tested in production.

10. Wake up time: Delay between the VCC(min) stable and the first accepted commands.

M24M02E-F

DC and AC parameters

DS14157 - Rev 2

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