10F200 datasheet(37/96 Pages) MICROCHIP

37 / 96 page

DS41239D-page 35

PIC10F200/202/204/206

7.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 7-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 7-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

7.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Figure 9-6). For

simplicity, this counter is being referred to as

“prescaler” throughout this data sheet.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x, etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a Reset, the prescaler contains all ‘0’s.

7.2.1

SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during pro-

gram execution). To avoid an unintended device Reset,

the following instruction sequence (Example 7-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

EXAMPLE 7-1:

CHANGING PRESCALER

(TIMER0

→ WDT)

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 7.2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

Increment Timer0 (Q4)

External Clock Input or

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0

T0 + 1

T0 + 2

Small pulse

misses sampling

External Clock/Prescaler

Output After Sampling

(3)

Prescaler Output(2)

(1)

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

CLRWDT

;Clear WDT

CLRF

TMR0

;Clear TMR0 & Prescaler

MOVLW

‘00xx1111’b ;These 3 lines (5, 6, 7)

OPTION

;are required only if

;desired

CLRWDT

;PS<2:0> are 000 or 001

MOVLW

‘00xx1xxx’b ;Set Postscaler to

OPTION

;desired WDT rate

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