PIC12F683-ESLASHMDQTP datasheet(34/176 Pages) MICROCHIP

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PIC12F683

DS41211D-page 32

4.2

Additional Pin Functions

Every

GPIO

the

PIC12F683

has

interrupt-on-change option and a weak pull-up option.

GP0 has an Ultra Low-Power Wake-up option. The

next three sections describe these functions.

4.2.1

ANSEL REGISTER

The ANSEL register is used to configure the Input

mode of an I/O pin to analog. Setting the appropriate

ANSEL bit high will cause all digital reads on the pin to

be read as ‘0’ and allow analog functions on the pin to

operate correctly.

The state of the ANSEL bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

4.2.2

WEAK PULL-UPS

Each of the GPIO pins, except GP3, has an individually

configurable internal weak pull-up. Control bits WPUx

enable or disable each pull-up. Refer to Register 4-4.

Each weak pull-up is automatically turned off when the

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset by the GPPU bit of the

OPTION register). A weak pull-up is automatically

enabled for GP3 when configured as MCLR and

disabled when GP3 is an I/O. There is no software

control of the MCLR pull-up.

4.2.3

INTERRUPT-ON-CHANGE

Each of the GPIO pins is individually configurable as an

interrupt-on-change pin. Control bits IOCx enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

GPIO. The ‘mismatch’ outputs of the last read are OR’d

together to set the GPIO Change Interrupt Flag bit

(GPIF) in the INTCON register (Register 2-3).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

Any read or write of GPIO. This will end the

mismatch condition, then,

Clear the flag bit GPIF.

A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and

allow flag bit GPIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor

Brown-out Reset. After these resets, the GPIF flag will

continue to be set if a mismatch is present.

TRISIO GPIO TRI-STATE REGISTER

U-0

R/W-1

R-1

R/W-1

—

—TRISIO5(2,3)

TRISIO4(2)

TRISIO3(1)

TRISIO2

TRISIO1

TRISIO0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5:4

TRISIO<5:4>: GPIO Tri-State Control bit

= GPIO pin configured as an input (tri-stated)

= GPIO pin configured as an output

bit 3

TRISIO<3>: GPIO Tri-State Control bit

Input only

bit 2:0

TRISIO<2:0>: GPIO Tri-State Control bit

= GPIO pin configured as an input (tri-stated)

= GPIO pin configured as an output

Note

TRISIO<3> always reads ‘1’.

TRISIO<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

TRISIO<5> always reads ‘1’ in RC and RCIO and EC modes.

Note:

If a change on the I/O pin should occur

when

any

GPIO

operation

being

executed, then the GPIF interrupt flag may

not get set.

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