ENC28J60T-CSLASHSP datasheet(58/96 Pages) MICROCHIP

58 / 96 page

ENC28J60

DS39662B-page 56

Preliminary

To enable flow control on the ENC28J60 in Full-Duplex

mode, the host controller must set the TXPAUS and

RXPAUS bits in the MACON1 register. Then, at any time

that the receiver buffer is running out of space, the host

controller should turn flow control on by writing the value

02h to the EFLOCON register. The hardware will period-

ically transmit pause frames loaded with the pause timer

value specified in the EPAUS registers. The host

controller can continue to transmit its own packets

without interfering with the flow control hardware.

When space has been made available for more packets

in the receive buffer, the host controller should turn flow

control off by writing the value 03h to the EFLOCON

loaded with a pause timer value of 0000h. When the

pause frame is received by the remote node, it will

resume normal network operations.

When RXPAUS is set in the MACON1 register and a

valid pause frame arrives with a non-zero pause timer

value,

the

ENC28J60

will

automatically

inhibit

transmissions.

the

host

controller

sets

the

ECON1.TXRTS bit to send a packet, the hardware will

simply wait until the pause timer expires before

attempting to send the packet and subsequently clearing

the TXRTS bit. Normally, the host controller will never

know that a pause frame has been received. However, if

it is desirable to the host controller to know when the

MAC is paused or not, it should set the PASSALL bit in

MACON1 and then manually interpret the pause control

frames which may arrive.

EFLOCON: ETHERNET FLOW CONTROL REGISTER

U-0

R-0

R/W-0

—

FULDPXS

FCEN1

FCEN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-3

Unimplemented: Read as ‘0’

bit 2

FULDPXS: Read-Only MAC Full-Duplex Shadow bit

= MAC is configured for Full-Duplex mode, FULDPX (MACON3<0>) is set

= MAC is configured for Half-Duplex mode, FULDPX (MACON3<0>) is clear

bit 1-0

FCEN1:FCEN0: Flow Control Enable bits

When FULDPXS = 1:

= Send one pause frame with a ‘0’ timer value and then turn flow control off

= Send pause frames periodically

= Send one pause frame then turn flow control off

= Flow control off

When FULDPXS = 0:

= Flow control on

= Flow control off

= Flow control on

= Flow control off

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