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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M58WR064B100ZB6T датащи(PDF) 27 Page - STMicroelectronics |
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M58WR064B100ZB6T датащи(HTML) 27 Page - STMicroelectronics |
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27 / 81 page  27/81 M58WR064T, M58WR064B the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select be- tween wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read oper- ation as result of a single address latch cycle. They can be set for 4 words, 8 words or continu- ous burst, where all the words are read sequential- ly. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- serts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition. CR14, CR5 and CR4 are reserved for future use. |
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