DSPIC33FJ12MC02ESS datasheet(170/284 Pages) MICROCHIP

170 / 284 page

dsPIC33FJ12MC201/202

DS70265B-page 168

Preliminary

15.7.2

TIMER OPERATION DURING CPU

IDLE MODE

When the CPU is placed in Idle mode and the QEI mod-

ule is configured in 16-bit Timer mode, the 16-bit timer

will operate if QEISIDL (QEICON<13>) = 0. This bit

defaults to a logic ‘0’ upon executing POR. To halt the

timer module during CPU Idle mode, QEISIDL should

be set to ‘1’.

If the QEISIDL bit is cleared, the timer will function

normally as if CPU Idle mode had not been entered.

15.8

Quadrature Encoder Interface

Interrupts

The Quadrature Encoder Interface can generate an

interrupt on occurrence of the following events:

• 16-bit up/down position counter rollover/underflow

• Detection of qualified index pulse

• CNTERR bit is set

• Timer period match event (overflow/underflow)

• Gate accumulation event

The QEI Interrupt Flag bit, QEIIF in the IFS3 register, is

asserted upon occurrence of any of these events. The

QEIIF bit must be cleared in software.

Enabling an interrupt is accomplished via the

respective enable bit, QEIIE, in the IEC3 register.

15.9

Control and Status Registers

The QEI module has four user-accessible registers,

accessible in either Byte or Word mode:

• Control/Status Register (QEICON) – Allows

control of the QEI operation and status flags

indicating the module state.

• Digital Filter Control Register (DFLTCON) –

Allows control of the digital input filter operation.

• Position Count Register (POSCNT) – Allows

reading and writing of the 16-bit position counter.

• Maximum Count Register (MAXCNT) – Holds a

value that is compared to the POSCNT counter in

some operations.

Note:

The

POSCNT

allows

byte

accesses,. However, reading the register

in Byte mode can result in partially

updated values in subsequent reads.

Either use Word mode reads/writes, or

ensure that the counter is not counting

during Byte operations.

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