DSPIC33FJ12MC02ESS datasheet(169/284 Pages) MICROCHIP

169 / 284 page

Preliminary

DS70265B-page 167

dsPIC33FJ12MC201/202

15.4

Programmable Digital Noise

Filters

The digital noise filter section of the module is

responsible for rejecting noise on the incoming

capture or quadrature signals. Schmitt Trigger inputs

and a 3-clock cycle delay filter combine to reject low-

level noise and large, short-duration noise spikes

that typically occur in noise prone applications, such

as a motor system.

The filter ensures that the filtered output signal is not

permitted to change until a stable value has been

registered for three consecutive clock cycles.

For the QEA, QEB and INDX pins, the clock divide

frequency for the digital filter is programmed by bits

QECK<2:0> (DFLTCON<6:4>), and are derived from

the base instruction cycle, TCY.

To enable the filter output for channels QEA, QEB and

INDX, the QEOUT bit must be ‘1’. The filter network for

all channels is disabled on POR.

15.5

Alternate 16-bit Timer/Counter

When the QEI module is not configured for the QEI

mode, QEIM<2:0> = 001, the module can be con-

figured as a simple 16-bit timer/counter. The setup and

control of the auxiliary timer is accomplished through

the QEICON SFR register. This timer functions identi-

cally to Timer1. The QEA pin is used as the timer clock

input.

When configured as a timer, the POSCNT register

serves as the Timer Count register, and the MAXCNT

Period register match occurs, the QEI interrupt flag is

asserted.

The only difference between the general purpose

timers and this timer is the external up/down input

select. When the UPDN pin is asserted high, the timer

increments up. When the UPDN pin is asserted low, the

timer is decremented.

The UPDN control/status bit (QEICON<11>) can be

used to select the count direction state of the Timer

UPDN = 0, the timer counts down.

In addition, control bit UPDN_SRC, (in QEICON<0>),

determines whether the timer count direction state is

based on the logic state written into the UPDN control/

status bit (QEICON<11>) or the QEB pin state:

• When UPDN_SRC = 1, the timer count direction

is controlled from the QEB pin.

• When UPDN_SRC = 0, the timer count direction

is controlled by the UPDN bit.

15.6

QEI Module Operation During CPU

Sleep Mode

During CPU Sleep mode, the following are true for the

QEI module:

• The QEI module is halted.

• The timer does not operate because the internal

clocks are disabled.

15.7

QEI Module Operation During CPU

Idle Mode

Since the QEI module can function as a Quadrature

Encoder Interface, or as a 16-bit timer, this section

describes operation of the module in both modes.

15.7.1

QEI OPERATION DURING CPU

IDLE MODE

When the CPU is placed in Idle mode, the QEI module

will operate if QEISIDL (QEICON<13>) = 0. This bit

defaults to a logic ‘0’ upon executing POR. To halt the

QEI module during CPU Idle mode, QEISIDL should

be set to ‘1’.

Note:

Changing the operational mode (for exam-

ple, from QEI to timer or vice versa) will not

affect the Timer/Position Count register

contents.

Note:

This alternate timer does not support the

External Asynchronous Counter mode of

operation. If the program uses an external

clock source, the clock will automatically

be synchronized to the internal instruction

cycle.

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