1998 Aug 26

10

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital

Converter (ADC)

TDA8768

Notes

1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:

edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF

capacitor.

edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF

capacitor.

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (peak-to-peak

value) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.

When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is

recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.

3. The

−3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a

full-scale sine wave.

4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:

where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all

harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:

6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input

signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (

−6dB

below full-scale for each input signal).

product.

THD

20 log

F

(2nd)

2

(3rd)

2

(4th)

2

(5th)

2

(6th)

2

+

+++

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