MCP3909 datasheet(14/40 Pages) MICROCHIP

14 / 40 page

MCP3909

DS22025A-page 14

3.5

Voltage Channel (CH1-,CH1+)

CH1- and CH1+ are the fully differential analog voltage

input channels for the voltage measurement. The linear

and specified region of these channels have a

maximum differential voltage of ±660 mV and a

maximum absolute voltage of ±1V, with respect to

AGND. Up to ±6V can be applied to these pins without

the risk of permanent damage.

Refer to Section 1.0 “Electrical Characteristics”.

3.6

Master Clear (MCLR)

MCLR controls the reset for both delta-sigma ADCs, all

digital registers, the SINC filters for each channel and

all accumulators post multiplier. The MCLR pin is also

used to change pin functionality and enter the serial

interface mode. A logic ‘0’ resets all registers and holds

both ADCs in a Reset condition. The charge stored in

both ADCs is flushed and their output is maintained to

0x0000h. The only block consuming power on the

digital power supply during Reset is the oscillator

circuit.

3.7

Reference (REFIN/OUT)

REFIN/OUT is the output for the internal 2.4V

reference. This reference has a typical temperature

coefficient of 15 ppm/°C and a tolerance of ±2%. In

addition, an external reference can also be used by

applying voltage to this pin within the specified range.

This pin requires appropriate bypass capacitors to

AGND, even when using the internal reference only.

Refer to Section 6.0 “Applications Information”.

3.8

Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry (ADCs, PGA, band gap reference, POR). To

ensure accuracy and noise cancellation, this pin must

be connected to the same ground as DGND, preferably

with a star connection. If an analog ground plane is

available, it is recommended that this device be tied to

this plane of the PCB. This plane should also reference

all other analog circuitry in the system.

3.9

Serial Clock Input or F2 Frequency

Control Pin

This dual function pin can act as either the serial clock

input for SPI communication or the F2 selection for the

high-frequency output and low-frequency output pin

ranges, changing the value of the constants FC and

HFC used in the device transfer function. FC and HFC

are the frequency constants that define the period of

the output pulses for the device.

3.10

Serial Data Input or F1 Frequency

Control Pin

This dual function pin can act as either the serial data

input for SPI communication or the F1 selection for the

high-frequency output and low-frequency output pin

ranges, changing the value of the constants FC and

HFC used in the device transfer function. FC and HFC

are the frequency constants that define the period of

the output pulses for the device.

3.11

Chip Select (CS) or F0 Frequency

Control Pin

This dual function pin can act as either the chip select

for SPI communication or the F0 selection for the high-

frequency output and low-frequency output pin ranges

by changing the value of the constants FC and HFC

used in the device transfer function. FC and HFC are

the frequency constants that define the period of the

output pulses for the device.

3.12

Gain Control Logic Pins (G1, G0)

G1 and G0 select the PGA gain (G) on Channel 0 from

four different values: 1, 2, 8 and 16.

3.13

Oscillator (OSC1, OSC2)

OSC1 and OSC2 provide the master clock for the

device. A resonant crystal or clock source with a similar

sinusoidal waveform must be placed across these pins

to ensure proper operation. The typical clock frequency

specified is 3.579545 MHz. However, the clock

frequency can be within the range of 1 MHz to 4 MHz

without disturbing measurement error. Appropriate

load capacitance should be connected to these pins for

proper operation.

A full-swing, single-ended clock source may be

connected to OSC1 with proper resistors in series to

ensure no ringing of the clock source due to fast

transient edges.

3.14

Serial Data Output or Negative

Power Output Logic Pin (NEG)

This dual function pin can act as either the serial data

output for SPI communication or NEG. NEG detects

the phase difference between the two channels and will

go to a logic ‘1’ state when the phase difference is

greater than 90° (i.e., when the measured real power is

negative). The output state is synchronous with the

rising-edge of HFOUT and maintains the logic ‘1’ until

the real power becomes positive again and HFOUT

shows a pulse.

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