MCP4822-ESLASHMS datasheet(19/36 Pages) MICROCHIP

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DS21953A-page 19

MCP4821/MCP4822

6.0

TYPICAL APPLICATIONS

The MCP482X devices are general purpose DACs

intended to be used in applications where a precision,

low-power DAC with moderate bandwidth and internal

voltage reference is required.

Applications generally suited for the MCP482X devices

include:

• Set Point or Offset Trimming

• Sensor Calibration

• Precision Selectable Voltage Reference

• Portable Instrumentation (Battery-Powered)

• Calibration of Optical Communication Devices

6.1

Digital Interface

The MCP482X devices utilize a 3-wire synchronous

serial protocol to transfer the DACs’ setup and output

values from the digital source. The serial protocol can

be interfaced to SPI™ or Microwire peripherals com-

mon on many microcontroller units (MCUs), including

Microchip’s PICmicro® MCUs and dsPIC® DSC family

of MCUs. In addition to the three serial connections

(CS, SCK and SDI), the LDAC signal synchronizes

when the serial settings are latched into the DAC’s

output from the serial input latch. Figure 6-1 illustrates

the required connections. Note that LDAC is active-low.

If desired, this input can be tied low to reduce the

required connections from 4 to 3. Write commands will

be latched directly into the output latch when a valid 16

clock transmission has been received and CS has

been raised.

6.2

Power Supply Considerations

The typical application will require a bypass capacitor

in order to filter high-frequency noise. The noise can be

induced onto the power supply's traces or as a result of

changes on the DAC's output. The bypass capacitor

helps to minimize the effect of these noise sources on

signal integrity. Figure 6-1 illustrates an appropriate

bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close to the device power pin (VDD) as possible (within

4mm).

The power source supplying these devices should be

as clean as possible. If the application circuit has sep-

arate digital and analog power supplies, AVDD and

AVSS should reside on the analog plane.

6.3

Output Noise Considerations

The voltage noise density (in µV/

√Hz) is illustrated in

Figure 2-9. This noise appears at VOUTX, and is prima-

rily a result of the internal reference voltage. Its 1/f

corner (fCORNER) is approximately 400 Hz.

Figure 2-10 illustrates the voltage noise (in mVRMS or

mVP-P). A small bypass capacitor on VOUTX is an

effective method to produce a single-pole Low-Pass

Filter (LPF) that will reduce this noise. For instance, a

bypass capacitor sized to produce a 1 kHz LPF would

result in an ENREF of about 100 µVRMS. This would be

necessary when trying to achieve the low DNL

performance (at G = 1) that the MCP482X devices are

capable of. The tested range for stability is .001µF thru

4.7 µF.

FIGURE 6-1:

Typical Connection

Diagram.

6.4

Layout Considerations

Inductively-coupled AC transients and digital switching

noise

can

degrade

the

output

signal

integrity,

potentially

masking

the

MCP482X

family’s

performance. Careful board layout will minimize these

effects and increase the Signal-to-Noise Ratio (SNR).

Bench testing has shown that a multi-layer board

utilizing a low-inductance ground plane, isolated inputs,

isolated outputs and proper decoupling are critical to

achieving the performance that the MCP482X devices

are

capable

providing.

Particularly

harsh

environments may require shielding of critical signals.

Breadboards

and

wire-wrapped

boards

are

not

recommended if low noise is desired.

VDD

AVSS

VOUTA

VOUTB

0.1 µF

0.1 µF 0.1 µF

VOUTA

VOUTB

SDI

CS1

SDO

SCK

LDAC

CS0

1µF

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