MCP4822-ESLASHMS datasheet(17/36 Pages) MICROCHIP

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DS21953A-page 17

MCP4821/MCP4822

5.0

SERIAL INTERFACE

5.1

Overview

The MCP482X family is designed to interface directly

with the SPI port, available on many microcontrollers,

and supports Mode 0,0 and Mode 1,1. Commands and

data are sent to the device via the SDI pin, with data

being clocked-in on the rising edge of SCK. The

communications are unidirectional and, thus, data

cannot be read out of the MCP482X devices. The CS

pin must be held low for the duration of a write com-

mand. The write command consists of 16 bits and is

used to configure the DAC’s control and data latches.

configure and load the DACA and DACB registers.

Refer

Figure 1-1

and

the

Electrical

Characteristics tables for detailed input and output tim-

ing specifications for both Mode 0,0 and Mode 1,1

operation.

5.2

Write Command

The write command is initiated by driving the CS pin

low, followed by clocking the four configuration bits and

the 12 data bits into the SDI pin on the rising edge of

SCK. The CS pin is then raised, causing the data to be

latched into the selected DAC’s input registers. The

MCP482X devices utilize a double-buffered latch struc-

ture to allow both DACA’s and DACB’s outputs to be

synchronized with the LDAC pin, if desired. Upon the

LDAC pin achieving a low state, the values held in the

DAC’s input registers are transferred into the DACs’

output registers. The outputs will transition to the value

and held in the DACX register.

All writes to the MCP482X devices are 16-bit words.

Any clocks past 16 will be ignored. The most signifi-

cant four bits are configuration bits. The remaining 12

bits are data bits. No data can be transferred into the

device with CS high. This transfer will only occur if 16

clocks have been transferred into the device. If the

rising edge of CS occurs prior, shifting of data into the

input registers will be aborted.

WRITE COMMAND REGISTER

bit 15

A/B: DACA or DACB Select bit

Write to DACB

Write to DACA

bit 14

—

Don’t Care

bit 13

GA: Output Gain Select bit

=1x (VOUT = VREF * D/4096)

=2x (VOUT = 2 * VREF * D/4096)

bit 12

SHDN: Output Power-down Control bit

Output Power-down Control bit

Output buffer disabled, Output is high-impedance

bit 11-0

D11:D0: DAC Data bits

12-bit number “D” which sets the output value. Contains a value between 0 and 4095.

Upper Half:

W-x

W-0

W-x

A/B

—

SHDN

D11

D10

bit 15

bit 8

Lower Half:

W-x

bit 7

bit 0

Legend

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

1 = bit is set

0 = bit is cleared

x = bit is unknown

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