MCP23017-ESLASHML datasheet(18/48 Pages) MICROCHIP

18 / 48 page

MCP23017/MCP23S17

DS21952B-page 18

IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)

R/W-0

U-0

BANK

MIRROR

SEQOP

DISSLW

HAEN

ODR

INTPOL

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

BANK: Controls how the registers are addressed

1 = The registers associated with each port are separated into different banks

0 = The registers are in the same bank (addresses are sequential)

bit 6

MIRROR: INT Pins Mirror bit

1 = The INT pins are internally connected

0 = The INT pins are not connected. INTA is associated with PortA and INTB is associated with PortB

bit 5

SEQOP: Sequential Operation mode bit.

1 = Sequential operation disabled, address pointer does not increment.

0 = Sequential operation enabled, address pointer increments.

bit 4

DISSLW: Slew Rate control bit for SDA output.

1 = Slew rate disabled.

0 = Slew rate enabled.

bit 3

HAEN: Hardware Address Enable bit (MCP23S17 only).

Address pins are always enabled on MCP23017.

1 = Enables the MCP23S17 address pins.

0 = Disables the MCP23S17 address pins.

bit 2

ODR: This bit configures the INT pin as an open-drain output.

1 = Open-drain output (overrides the INTPOL bit).

0 = Active driver output (INTPOL bit sets the polarity).

bit 1

INTPOL: This bit sets the polarity of the INT output pin.

1 = Active-high.

0 = Active-low.

bit 0

Unimplemented: Read as ‘0’.

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