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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP23017-E/ML датащи(PDF) 14 Page - Microchip Technology |
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MCP23017-E/ML датащи(HTML) 14 Page - Microchip Technology |
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14 / 48 page  MCP23017/MCP23S17 DS21952B-page 14 © 2007 Microchip Technology Inc. 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-on- change feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 GPINT7:GPINT0: General purpose I/O interrupt-on-change bits <7:0> 1 = Enable GPIO input pin for interrupt-on-change event. 0 = Disable GPIO input pin for interrupt-on-change event. Refer to INTCON and GPINTEN. |
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