PS700 datasheet(29/38 Pages) MICROCHIP

29 / 38 page

 2004 Microchip Technology Inc.

DS21760F-page 29

PS700

5.0

CAL/SETUP MODE AND

REGISTERS

Cal/Setup mode allows the designer to reprogram the

default SMBus address and/or change the calibration

parameters programmed at the factory for band gap,

voltage reference and main oscillator trim values.

Entering Cal/Setup mode requires the host to request

three consecutive and specific incorrect SMBus

addresses with no interruptions between requests.

These addresses are:

Addr1

HEX 50

Addr2

HEX 52

Addr3

HEX 74

After each address is sent, the PS700 will NACK the

address. Once the sequence is complete, the PS700

will enter Cal/Setup mode and allow access to the

Cal/Setup registers located in memory Bank 2.

To exit Cal/Setup mode, re-enter the same address

sequence or power-down the part. The PS700 will

always power-up with Cal/Setup mode disabled.

The following registers are only available in Cal/Setup

mode.

5.1

Cal/Setup Mode Registers

SMBAdd: SMBus ADDRESS REGISTERS (ADDRESS 80 HEX/128 DECIMAL)

VBGT: BAND GAP TRIM REGISTER (ADDRESS 81 HEX/129 DECIMAL)

SMBAdd

Reserved

bit 7

bit 0

bit 7-1

SMBAdd: SMBus Address Register bits

The value placed in bits <7:1> of this register defines the SMBus address for this device.

bit 0

Reserved: Reserved bit location

Legend:

‘1’ = Bit is set

‘0’ = Bit is cleared

R = Reserved bit

Reserved

VBGT

bit 7

bit 0

bit 7-4

Reserved: Reserved bit location

bit 3-0

VBGT: Band Gap Voltage Trim bits

This value is set by the factory.

Legend:

‘1’ = Bit is set

‘0’ = Bit is cleared

R = Reserved bit

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