SCF5249VM140 datasheet(26/56 Pages) FREESCALE

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SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Signal Descriptions

Freescale Semiconductor

8.19.5 Processor Status

The processor status pins, PST0_GPIO59, PST1_GPIO60, PST2_GPIO61, and PST3_GPIO62, indicate

the SCF5249 processor status. During debug mode, the timing is synchronous with the processor clock

(PSTCLK) and the status is not related to the current bus transfer. .

8.20 BDM/JTAG Signals

The SCF5249 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed

with background debug pins.

8.20.1 Test Clock

TCK is the dedicated JTAG test logic clock that is independent of the SCF5249 processor clock. Various

JTAG operations occur on the rising or falling edge of TCK. The internal JTAG controller logic is designed

such that holding TCK high or low for an indefinite period of time will not cause the JTAG test logic to

lose state information. If TCK will not be used, it should be tied to ground.

Table 14. Processor Status Signal Encodings

PST[3:0]

Definition

(HEX)

(BINARY)

0000

Continue execution

0001

Begin execution of an instruction

0010

Reserved

0011

Entry into user-mode

0100

Begin execution of PULSE and WDDATA instructions

0101

Begin execution of taken branch or Synch_PC1

0110

Reserved

0111

Begin execution of RTE instruction

1000

Begin 1-byte data transfer on DDATA

1001

Begin 2-byte data transfer on DDATA

1010

Begin 3-byte data transfer on DDATA

1011

Begin 4-byte data transfer on DDATA

1100

Exception processing2

1101

Emulator mode entry exception processing2

1110

Processor is stopped, waiting for interrupt2

1111

Processor is halted2

Notes:

Rev. B enhancement.

These encodings are asserted for multiple cycles.

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