AD9956-VCOSLASHPCB datasheet(17/32 Pages) AD

17 / 32 page

AD9956

Rev. B | Page 17 of 32

DAC

CHARGE

PUMP

REF

OSC

DDS

÷N

÷M

÷R

LPF

VCO

CML

DRIVER

PHASE FREQUENCY

DETECTOR

EXTERNAL

REFERENCE

622MHz

CLOCK1

CLOCK2

AD9956

Figure 25. Optical Networking Clock

CHARGE

PUMP

PLLREF

PLLOSC

÷N

VCO

DAC

DDS

PHASE

FREQUENCY

DETECTOR

≤650MHz

LPF

Figure 26. Direct Upconversion

APPLICATION CIRCUIT EXPLANATIONS

Dual-Clock Configuration

In this loop, M = 1, N = 16, and R = 4. The DDS tuning word is

also equal to ¼ so that the frequency of CLOCK 1’ equals the

frequency of CLOCK 1. Phase adjustments in the DDS provide

a 14-bit programmable rising edge skew capability of CLOCK

1’ with respect to CLOCK 1 (see Figure 22).

Fractional-Divider Loop

This loop offers the precise frequency division (48-bit) of the

DDS in the feedback path as well as the frequency sweeping

capability of the DDS. Programming the DDS to sweep from

24 MHz to 25 MHz sweeps the output of the VCO from

2.7 GHz to 2.6 GHz. The reference in this case is a simple

crystal (see Figure 23).

LO and Baseband Modulation Generation

Using the AD9956’s PLL section to generate an LO and the

DDS portion to generate a modulated baseband, this circuit

uses an external mixer to perform some simple modulation at

RF frequencies (see Figure 24).

Optical Networking Clock

This is the AD9956 configured as an optical networking clock.

The loop can be used to generate a 622 MHz clock for OC12.

The DDS can be programmed to output 8 kHz to serve as a base

reference for other circuits in the subsystem (see Figure 25).

Direct Upconversion

The AD9956 is configured to use the DDS as a precision refer-

ence to the PLL loop. Since the VCO is < 655 MHz, it can be

fed straight into the phase frequency detector feedback input

(with the divider enabled), as seen in Figure 26.

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