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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9912A/PCBZ датащи(PDF) 6 Page - Analog Devices |
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AD9912A/PCBZ датащи(HTML) 6 Page - Analog Devices |
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6 / 38 page  Data Sheet AD9912 SPECIFICATIONS analog.com Rev. G | 6 of 38 Table 2. (Continued) Parameter Min Typ Max Unit Test Conditions/Comments Output Offset 0.6 μA Voltage Compliance Range AVSS − 0.50 +0.5 AVSS + 0.50 V Outputs connected to a transformer whose center tap is grounded Wideband SFDR See the Typical Performance Characteristics section 20.1 MHz Output −79 dBc 0 MHz to 500 MHz 98.6 MHz Output −67 dBc 0 MHz to 500 MHz 201.1 MHz Output −61 dBc 0 MHz to 500 MHz 398.7 MHz Output −59 dBc 0 MHz to 500 MHz Narrow-Band SFDR See the Typical Performance Characteristics section 20.1 MHz Output −95 dBc ±250 kHz 98.6 MHz Output −96 dBc ±250 kHz 201.1 MHz Output −91 dBc ±250 kHz 398.7 MHz Output −86 dBc ±250 kHz DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down 15 µs Time Required to Leave Power-Down 18 µs Reset Assert to High-Z Time for S1 to S4 Configuration Pins 60 ns Time from rising edge of RESET to high-Z on the S1, S2, S3, S4 configuration pins SERIAL PORT TIMING SPECIFICATIONS SCLK Clock Rate (1/tCLK ) 25 50 MHz Refer to Figure 56 for all write-related serial port parameters; maximum SCLK rate for readback is governed by tDV SCLK Pulse Width High, tHIGH 8 ns SCLK Pulse Width Low, tLOW 8 ns SDO/SDIO to SCLK Setup Time, tDS 1.93 ns SDO/SDIO to SCLK Hold Time, tDH 1.9 ns SCLK Falling Edge to Valid Data on SDIO/SDO, tDV 11 ns Refer to Figure 54 CSB to SCLK Setup Time, tS 1.34 ns CSB to SCLK Hold Time, tH −0.4 ns CSB Minimum Pulse Width High, tPWH 3 ns IO_UPDATE Pin Setup Time (from SCLK Rising Edge of the Final Bit) tCLK sec tCLK = period of SCLK in Hz IO_UPDATE Pin Hold Time tCLK sec tCLK = period of SCLK in Hz PROPAGATION DELAY FDBK_IN to HSTL Output Driver 2.8 ns FDBK_IN to HSTL Output Driver with 2× Frequency Multiplier Enabled 7.3 ns FDBK_IN to CMOS Output Driver 8.0 ns S-divider bypassed FDBK_IN Through S-Divider to CMOS Output Driver 8.6 ns Frequency Tuning Word Update: IO_UPDATE Pin Rising Edge to DAC Output 60/fS ns fS = system clock frequency in GHz |
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