AD9912ASLASHPCBZ datasheet(36/38 Pages) AD

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Data Sheet

AD9912

I/O REGISTER DESCRIPTIONS

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Rev. G | 36 of 38

DOUBLER AND OUTPUT DRIVERS (REGISTER 0X0200 TO REGISTER 0X0201)

Table 32.

Bits

Bit Name

Description

OPOL

Output polarity. Setting this bit inverts the HSTL driver output polarity.

[3:2]

Reserved

Reserved.

[1:0]

HSTL output doubler

HSTL output doubler.

01 = doubler disabled.

10 = doubler enabled. When using doubler, Bit 5 in Register 0x0010 must also be set to 1.

Table 33.

Bits

Bit Name

Description

CMOS mux

This bit allows the user to select whether the CMOS driver output is divided by the S-divider.

0 = S-divider input sent to CMOS driver.

1 = S-divider output sent to CMOS driver. See Figure 39.

CALIBRATION (USER-ACCESSIBLE TRIM) (REGISTER 0X0400 TO REGISTER 0X0410)

Table 34.

Bits

Bit Name

Description

[7:0]

DAC full-scale current

DAC full-scale current, Bits[7:0]. See the Digital-to-Analog (DAC) Output section.

Table 35.

Bits

Bit Name

Description

[9:8]

DAC full-scale current

DAC full-scale current, Bits[9:8]. See Register 0x040B.

HARMONIC SPUR REDUCTION (REGISTER 0X0500 TO REGISTER 0X0509)

See the Harmonic Spur Reduction section.

Table 36.

Bits

Bit Name

Description

HSR-A enable

Harmonic Spur Reduction A enable.

Amplitude gain × 2

Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.

[5:4]

Reserved

Reserved.

[3:0]

Spur A harmonic

Spur A Harmonic 1 to Spur A Harmonic 15. Allows user to choose which harmonic to eliminate.

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