MCP616 datasheet(14/30 Pages) MICROCHIP

14 / 30 page

MCP616/7/8/9

DS21613B-page 14

4.5

MCP618 Chip Select (CS)

The MCP618 is a single op amp with Chip Select (CS).

When CS is pulled high, the supply current drops to

50 nA (typ.) and flows through the CS pin to VSS. When

this happens, the amplifier output is put into a high-

impedance state. By pulling CS low, the amplifier is

enabled. If the CS pin is left floating, the amplifier may

not operate properly. Figure 1-1 shows the output

voltage and supply current response to a CS pulse.

4.6

Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high-frequency performance. It may use a bulk

capacitor (i.e., 1 µF or larger) within 100 mm to provide

large, slow currents. This bulk capacitor is not required

and can be shared with other analog parts.

4.7

Unused Op Amps

An unused op amp in a quad package (MCP619)

should be configured as shown in Figure 4-6. Both

circuits prevent the output from toggling and causing

crosstalk. Circuit A can use any reference voltage

between the supplies, provides a buffered DC voltage

and minimizes the supply current draw of the unused

amp.

Circuit

minimizes

the

number

components, but may draw a little more supply current

for the unused op amp.

FIGURE 4-6:

Unused Op Amps.

4.8

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP616/7/8/9 family’s bias current at 25°C (1 pA,

typ.).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example is shown below in Figure 4-7.

FIGURE 4-7:

Example Guard Ring Layout

for Inverting Gain.

Non-inverting Gain and Unity Gain Buffer:

Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

Connect the guard ring to the inverting input

pin (VIN–). This biases the guard ring to the

common mode input voltage.

Inverting Gain and Transimpedance gain (con-

vert current to voltage, such as photo detectors)

amplifiers:

Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., VDD/2 or ground).

Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB

surface.

VDD

¼ MCP619 (A)

¼ MCP619 (B)

Guard Ring

VIN–VIN+

VSS

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