MSC7119 datasheet(47/56 Pages) FREESCALE

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Hardware Design Considerations

MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6

Freescale Semiconductor

3.4.3

Boot

After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device operates

slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the device operating at a higher

speed. The MSC7119 can boot from an external host through the HDI16 or download a user program through the I2C port. The

boot operating mode is set by configuring the BM[0–3] signals sampled at the rising edge of PORESET, as shown in Table 35.

See the MSC711x Reference Manual for details of boot program operation.

3.4.3.1

HDI16 Boot

If the MSC7119 device boots from an external host through the HDI16, the port is configured as follows:

•

Operate in Non-DMA mode.

•

Operate in polled mode on the device side.

•

Operate in polled mode on the external host side.

•

External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as

the least significant.

Table 35. Boot Mode Source Selection

BM[3–0]

Boot

Port

Input Clock

Frequency

Clock

Divide

PLL

CKSEL

RNG

Bit

Core Clock

Frequency

Comments

HDI Boot Modes

0000

HDI16

< Fmax

N/A

< Fmax

Not clocked by the PLL.

Can boot as 8- or 16-bit HDI.

0101

HDI16

22.2-25 MHz

266–300 MHz

Can boot as 8- or 16-bit HDI.

0010

HDI16

25-33.3 MHz

200–266 MHz

0111

HDI16

33-66 MHz

132–264 MHz

0100

HDI16

44.3-50 MHz

266–300 MHz

SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins

1000

SPI (SW)

< Fmax

N/A

< Fmax

The boot program automatically

determines whether EEPROM

or Flash memory.

1001

SPI (SW)

15.6-25 MHz

133–212.5 MHz

1010

SPI (SW)

33-50 MHz

132–200 MHz

1011

SPI (SW)

44.3-75 MHz

133–225 MHz

SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins

1100

SPI (SW)

< Fmax

N/A

< Fmax

Boots through different set of

pins.

I2C Boot Modes

0001

I2C

< 100 MHz

N/A

< 100 MHz

Not clocked by the PLL.

I2C is limited to a maximum bit

rate of 400 Kbps. With a clock

divider of 128, this limits the

maximum input clock frequency

to 100 MHz.

Reserved

0011

Reserved

—

0110

Reserved

—

1101

Reserved

—

1110

Reserved

—

1111

Reserved

—

Notes:

The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.

The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.

Fmax is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.

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